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1364847
2017 Mar 11
2
Is there a way to know the target's L1 data cache line size?
Thank you! Is this information available programmatically through some
LLVM API, so that next time some hardware manufacturer does some crazy
experiment, my code can be automatically compatible with it as soon as
LLVM is?
Le 11/03/2017 à 13:38, Bruce Hoult a écrit :
> PowerPC G5 (970) and all recent IBM Power have 128 byte cache lines. I
> believe Itanium is also 128.
>
> Intel