search for: 4cf51bee

Displaying 3 results from an estimated 3 matches for "4cf51bee".

2015 Jul 31
0
[LLVMdev] TableGen Register Class not matching for MI in 3.6
Hi Ryan, Could you check where those moves come from? In particular, is this the product of the instruction selection process? You use -print-machineinstrs to see when it is inserted. Thanks, -Quentin > On Jul 30, 2015, at 2:02 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > In LLVM 3.6, > > We have an instruction that uses a register class that is defined of
2015 Jul 30
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
In LLVM 3.6, We have an instruction that uses a register class that is defined of several different reg classes. In 3.4 this works fine but in 3.6 this is broken. For example, I have a mov instruction. mov can be executed between different register types (ie gpr, index, base, etc..) In 3.4, we would get something like this: mov @a, %b1 // moving this immediate to a base register, which is
2015 Jul 31
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...opers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150731/4cf51bee/attachment.html>