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2011 Oct 07
0
[LLVMdev] Vlang - TR : LLVM and VHDL simulation
...rently working on Verilog fronted and I am looking for somebody with VHDL interest to join the Vlang project. >Greetings >Jonas Cheers, Pawel -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111006/4be30efd/attachment.html>