Displaying 20 results from an estimated 29 matches for "48r".
Did you mean:
48
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...rived fromĀ
16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
register: %vreg17 +[16r,352r:0)
32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg1...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...;def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
> register: %vreg17 +[16r,352r:0)
> 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
> R600_Re...
2012 Aug 28
5
[LLVMdev] Assert in LiveInterval update
Andy, Lang,
Thanks for the suggestion.
I have spent more time with it today, and I do see some strange things in
liveness update. I am not at the actual cause yet, but here is what I got so
far:
I have the following live ranges when I start scheduling a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>; IntRegs:%vreg27
12B %v...
2012 Aug 30
0
[LLVMdev] Assert in LiveInterval update
...the suggestion.
>
>
> I have spent more time with it today, and I do see some strange things in
> liveness update. I am not at the actual cause yet, but here is what I got
> so
> far:
>
> I have the following live ranges when I start scheduling a region:
>
> R2 = [0B,48r:0)[352r,416r:5)...
> R3 = [0B,48r:0)[368r,416r:5)...
> R4 = [0B,32r:0)[384r,416r:4)...
> R5 = [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B...
2012 Aug 31
2
[LLVMdev] Assert in LiveInterval update
...ora.org> wrote:
Andy, Lang,
Thanks for the suggestion.
I have spent more time with it today, and I do see some strange things in
liveness update. I am not at the actual cause yet, but here is what I got so
far:
I have the following live ranges when I start scheduling a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>;...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...suggestion.
>
>
> I have spent more time with it today, and I do see some strange
> things in liveness update. I am not at the actual cause yet, but here
> is what I got so
> far:
>
> I have the following live ranges when I start scheduling a region:
>
> R2 = [0B,48r:0)[352r,416r:5)...
> R3 = [0B,48r:0)[368r,416r:5)...
> R4 = [0B,32r:0)[384r,416r:4)...
> R5 = [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B %vreg27<def> =...
2012 Aug 31
0
[LLVMdev] Assert in LiveInterval update
...ora.org> wrote:
Andy, Lang,
Thanks for the suggestion.
I have spent more time with it today, and I do see some strange things in
liveness update. I am not at the actual cause yet, but here is what I got so
far:
I have the following live ranges when I start scheduling a region:
R2 = [0B,48r:0)[352r,416r:5)...
R3 = [0B,48r:0)[368r,416r:5)...
R4 = [0B,32r:0)[384r,416r:4)...
R5 = [0B,32r:0)[400r,416r:4)...
I schedule the following instruction (48B):
0B BB#0: derived from LLVM BB %entry
Live Ins: %R0 %R1 %D1 %D2
8B %vreg27<def> = COPY %R1<kill>;...
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...t; I have spent more time with it today, and I do see some strange
>> things in liveness update. I am not at the actual cause yet, but here
>> is what I got so
>> far:
>>
>> I have the following live ranges when I start scheduling a region:
>>
>> R2 = [0B,48r:0)[352r,416r:5)...
>> R3 = [0B,48r:0)[368r,416r:5)...
>> R4 = [0B,32r:0)[384r,416r:4)...
>> R5 = [0B,32r:0)[400r,416r:4)...
>>
>> I schedule the following instruction (48B):
>>
>> 0B BB#0: derived from LLVM BB %entry
>> Live Ins: %R0 %R1...
2012 Aug 28
0
[LLVMdev] Assert in LiveInterval update
On Aug 28, 2012, at 8:18 AM, Sergei Larin <slarin at codeaurora.org> wrote:
>
> I've described that issue (see below) when you were out of town... I think
> I am getting more context on it. Please take a look...
>
> So, in short, when the new MI scheduler performs move of an instruction, it
> does something like this:
>
> // Move the instruction to its new
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...-def,dead>
192B NOP
# End machine code for function addproddivConst.
handleMove 64B -> 104B: %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
%vreg4: [64r,128r:0) 0 at 64r
--> [104r,128r:0) 0 at 104r
%vreg3: [48r,64r:0) 0 at 48r
--> [48r,104r:0) 0 at 48r
# *** IR Dump After Machine Instruction Scheduler ***:
# Machine code for function addproddivConst: Post SSA
Function Live Ins: %FA_ROFF1 in %vreg0
0B BB#0: derived from LLVM BB %entry
Live Ins: %FA_ROFF1
16B %...
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
...y, and I do see some strange
> >> things in liveness update. I am not at the actual cause yet, but
> here
> >> is what I got so
> >> far:
> >>
> >> I have the following live ranges when I start scheduling a region:
> >>
> >> R2 = [0B,48r:0)[352r,416r:5)...
> >> R3 = [0B,48r:0)[368r,416r:5)...
> >> R4 = [0B,32r:0)[384r,416r:4)...
> >> R5 = [0B,32r:0)[400r,416r:4)...
> >>
> >> I schedule the following instruction (48B):
> >>
> >> 0B BB#0: derived from LLVM BB %entry
&g...
2013 Oct 10
1
[LLVMdev] Missing optimization - constant parameter
...ING INTERVALS ***********
> entry:
> 64B %RDI<def> = COPY %vreg0; GR64:%vreg0
> Considering merging %vreg0 with %RDI
> Can only merge into reserved registers.
> Remat: %RDI<def> = MOV64ri 12345123400
> Shrink: [32r,64r:0) 0 at 32r
> Shrunk: [32r,48r:0) 0 at 32r
> Trying to inflate 0 regs.
> ********** INTERVALS **********
> %vreg0 = [32r,48r:0) 0 at 32r
> RegMasks: 80r
>
> Jakob, what does "can only merge into reserved registers" mean in this instance. I don't see any reason for it not to do the merge.
The c...
2012 Sep 03
2
[LLVMdev] Assert in LiveInterval update
...the suggestion.
>
>
> I have spent more time with it today, and I do see some strange things in
> liveness update. I am not at the actual cause yet, but here is what I got
> so
> far:
>
> I have the following live ranges when I start scheduling a region:
>
> R2 = [0B,48r:0)[352r,416r:5)...
> R3 = [0B,48r:0)[368r,416r:5)...
> R4 = [0B,32r:0)[384r,416r:4)...
> R5 = [0B,32r:0)[400r,416r:4)...
>
> I schedule the following instruction (48B):
>
> 0B BB#0: derived from LLVM BB %entry
> Live Ins: %R0 %R1 %D1 %D2
> 8B...
2013 Oct 10
0
[LLVMdev] Missing optimization - constant parameter
...** Function: caller
********** JOINING INTERVALS ***********
entry:
64B %RDI<def> = COPY %vreg0; GR64:%vreg0
Considering merging %vreg0 with %RDI
Can only merge into reserved registers.
Remat: %RDI<def> = MOV64ri 12345123400
Shrink: [32r,64r:0) 0 at 32r
Shrunk: [32r,48r:0) 0 at 32r
Trying to inflate 0 regs.
********** INTERVALS **********
%vreg0 = [32r,48r:0) 0 at 32r
RegMasks: 80r
Jakob, what does "can only merge into reserved registers" mean in this
instance. I don't see any reason for it not to do the merge.
On Mon, Aug 5, 2013 at 11:19 AM,...
2012 Aug 28
2
[LLVMdev] Assert in LiveInterval update
Andy,
I've described that issue (see below) when you were out of town... I think
I am getting more context on it. Please take a look...
So, in short, when the new MI scheduler performs move of an instruction, it
does something like this:
// Move the instruction to its new location in the instruction stream.
MachineInstr *MI = SU->getInstr();
if (IsTopNode) {
2013 Aug 05
2
[LLVMdev] Missing optimization - constant parameter
On Aug 5, 2013, at 8:34 AM, Maurice Marks <maurice.marks at gmail.com> wrote:
> Are you sure that's it? I commented that block out, rebuilt llvm 3.3, and it still duplicates the constant.
> My concern is that long constant loads increase code size and if they can be avoided by better targeting it would be a win. My project's application of llvm tends to use a lot of long
2012 Aug 30
0
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
On Aug 30, 2012, at 1:20 PM, Arnold Schwaighofer <arnolds at codeaurora.org> wrote:
> The code in collectRanges() does:
>
> // Collect ranges for register units. These live ranges are computed on
> // demand, so just skip any that haven't been computed yet.
> if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
> for (MCRegUnitIterator Units(Reg,
2012 Aug 30
2
[LLVMdev] MC Register mapping question (MCRegUnitIterator )
The code in collectRanges() does:
// Collect ranges for register units. These live ranges are computed on
// demand, so just skip any that haven't been computed yet.
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
for (MCRegUnitIterator Units(Reg, &TRI); Units.isValid(); ++Units)
if (LiveInterval *LI = LIS.getCachedRegUnit(*Units))
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...m/intel/tinycrypt/blob/master/lib/source/ecc_dh.c#L139
Thanks,
Prathamesh
-------------- next part --------------
PreferIndirect: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48...