search for: 4622940134a5

Displaying 7 results from an estimated 7 matches for "4622940134a5".

2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...<jroedel at suse.de> > Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org > --- > arch/x86/kernel/head_64.S | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE >...
2020 Aug 29
2
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...<jroedel at suse.de> > Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org > --- > arch/x86/kernel/head_64.S | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > index 08412f308de3..4622940134a5 100644 > --- a/arch/x86/kernel/head_64.S > +++ b/arch/x86/kernel/head_64.S > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > orl $X86_CR4_LA57, %ecx > 1: > #endif > + > + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE >...
2020 Aug 24
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...APs. Signed-off-by: Joerg Roedel <jroedel at suse.de> Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org --- arch/x86/kernel/head_64.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 08412f308de3..4622940134a5 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) orl $X86_CR4_LA57, %ecx 1: #endif + + ALTERNATIVE "jmp .Lstartup_write_cr4", "", X86_FEATURE_FSGSBASE + + /* Early exception handling uses FSGSBAS...
2020 Aug 31
0
[PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early
...; Link: https://lore.kernel.org/r/20200724160336.5435-38-joro at 8bytes.org > > --- > > arch/x86/kernel/head_64.S | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S > > index 08412f308de3..4622940134a5 100644 > > --- a/arch/x86/kernel/head_64.S > > +++ b/arch/x86/kernel/head_64.S > > @@ -153,6 +153,13 @@ SYM_CODE_START(secondary_startup_64) > > orl $X86_CR4_LA57, %ecx > > 1: > > #endif > > + > > + ALTERNATIVE "jmp .Lstartup_write_cr4",...
2020 Aug 24
0
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
...ad64.c +++ b/arch/x86/kernel/head64.c @@ -39,6 +39,7 @@ #include <asm/realmode.h> #include <asm/extable.h> #include <asm/trapnr.h> +#include <asm/sev-es.h> /* * Manage page tables very early on. diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 4622940134a5..12bf6f11fd83 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -95,6 +95,13 @@ SYM_CODE_START_NOALIGN(startup_64) .Lon_kernel_cs: UNWIND_HINT_EMPTY + /* Setup IDT - Needed for SEV-ES */ + pushq %rsi + /* early_idt_setup - physbase as first parameter */ + leaq _text(%ri...
2020 Aug 24
96
[PATCH v6 00/76] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de> Hi, here is the new version of the SEV-ES client enabling patch-set. It is based on the latest tip/master branch and contains the necessary changes. In particular those ar: - Enabling CR4.FSGSBASE early on supported processors so that early #VC exceptions on APs can be handled. - Add another patch (patch 1) to fix a KVM frame-size build
2020 Jul 24
86
[PATCH v5 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de> Hi, here is a rebased version of the latest SEV-ES patches. They are now based on latest tip/master instead of upstream Linux and include the necessary changes. Changes to v4 are in particular: - Moved early IDT setup code to idt.c, because the idt_descr and the idt_table are now static - This required to make stack protector work early (or