Displaying 6 results from an estimated 6 matches for "460kbps".
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2014 Jun 24
2
[PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers
...nd invalidated explicitly at the
> appropriate places. Introduce two small helpers to make things
> easy for TTM-based drivers.
Have you run this with DMA API debugging enabled? I suspect you haven't,
and I recommend that you do.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
2014 Jun 26
2
[PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers
...utterly
meaningless.
The lowmem/highmem split is entirely a software concept and is completely
adjustable. An extreme example is that you can boot any platform with
more than 32MB of memory with 32MB of lowmem and the remainder as
highmem.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
2014 Jun 25
2
[PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers
On Tue, Jun 24, 2014 at 6:25 AM, Lucas Stach <l.stach at pengutronix.de> wrote:
> Am Dienstag, den 24.06.2014, 14:27 +0200 schrieb Maarten Lankhorst:
>> op 24-06-14 14:23, Alexandre Courbot schreef:
>> > On Tue, Jun 24, 2014 at 7:55 PM, Alexandre Courbot <acourbot at nvidia.com> wrote:
>> >> On 06/24/2014 07:33 PM, Alexandre Courbot wrote:
>>
2014 Jun 24
1
[PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers
...es and/or refuse to discuss their requirements when
interfaces don't quite do what they want - or worse, refuse to listen
to objections.
As I say, it's disrespectful to your fellow kernel developers to abuse
well defined interfaces.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
2014 Jun 24
3
[PATCH v2 2/3] drm/ttm: introduce dma cache sync helpers
On 06/24/2014 07:33 PM, Alexandre Courbot wrote:
> On 06/24/2014 07:02 PM, Russell King - ARM Linux wrote:
>> On Tue, Jun 24, 2014 at 06:54:26PM +0900, Alexandre Courbot wrote:
>>> From: Lucas Stach <dev at lynxeye.de>
>>>
>>> On architectures for which access to GPU memory is non-coherent,
>>> caches need to be flushed and invalidated explicitly
2014 Jun 24
4
[PATCH v2 0/3] drm/ttm: nouveau: memory coherency for ARM
For this v2 I have fixed the patches that are non-controversial (all Lucas' :))
and am resubmitting them in the hope that they will get merged. This will
just leave the issue of Nouveau system-memory buffers mapping to be solved.
This issue is quite complex, so let me summarize the situation and the data
I have at hand. ARM caching is like a quantum world where Murphy's law
constantly