Displaying 7 results from an estimated 7 matches for "432r".
Did you mean:
432
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...ts.llvm.org
> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
-------------- next part --------------
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 at 128r
%0 [48...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...gt;; R600_Reg128:%vreg1 R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT: [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
416B%vreg48<def> = COPY %vreg3<kill&g...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...0_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT:
> [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
> 416B%vreg48<def>...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...ll>, %T1_X<imp-use,kill>, %T2_W<imp-use,kill>, %T2_Z<imp-use,kill>, %T2_Y<imp-use,kill>, %T2_X<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0BBB#0 T1_W#0 T1_Z#0 T1_Y#0 T1_X#0
Created 4 new intervals.
********** INTERVALS **********
T1_W = [0B,64r:0)[416r,432r:1) 0 at 0B-phi 1 at 416r
T1_X = [0B,16r:0)[368r,432r:1) 0 at 0B-phi 1 at 368r
T1_Y = [0B,32r:0)[384r,432r:1) 0 at 0B-phi 1 at 384r
T1_Z = [0B,48r:0)[400r,432r:1) 0 at 0B-phi 1 at 400r
%vreg0 = [64r,416r:0) 0 at 64r
%vreg1 = [48r,400r:0) 0 at 48r
%vreg2 = [32r,384r:0) 0 at 32r
%vreg3 = [16r,3...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2