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...ddress_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); > writel(msg->data, base + PCI_MSIX_ENTRY_DATA); > ...... > >> shouldn't. I don't know all the details about MSI, but doesn't the CPU >> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >> chipset board. Both quite ancient... > > MSI in x86 always send to specific interrupt address(0xfeexxxx), most x86 CPU > should support MSI, but I am not sure, I don't know hardware much. To put things in perspective, P200MMX was released in early 1997. It looks like the PCI...

...DDR); >>> writel(msg->data, base + PCI_MSIX_ENTRY_DATA); >>> ...... >>> >>>> shouldn't. I don't know all the details about MSI, but doesn't the CPU >>>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >>>> chipset board. Both quite ancient... >>> >>> MSI in x86 always send to specific interrupt address(0xfeexxxx), most x86 CPU >>> should support MSI, but I am not sure, I don't know hardware much. >> >> To put things in perspective, P200MMX w...

...I_MSIX_ENTRY_UPPER_ADDR); >> writel(msg->data, base + PCI_MSIX_ENTRY_DATA); >> ...... >> >>> shouldn't. I don't know all the details about MSI, but doesn't the CPU >>> or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX >>> chipset board. Both quite ancient... >> >> MSI in x86 always send to specific interrupt address(0xfeexxxx), most x86 CPU >> should support MSI, but I am not sure, I don't know hardware much. > > To put things in perspective, P200MMX was released in early 19...

.... -Brian On Fri, Jul 4, 2014 at 1:59 AM, Yijing Wang <wangyijing at huawei.com> wrote: >>>> There is a NVIDIA G96 GPU (which is PCIe only) hanging off of a PCIe >>>> <-> PCI bridge (all on one card), which is plugged into a motherboard >>>> with the 430FX chipset (PCI 2.0 supported). >>>> >>>> The GPU PCI device, of course, has full support for MSI. However my >>>> understanding is that MSI won't actually work here. This is confirmed >>>> by the fact that if we let nouveau enable MSI, the device do...

On 2014/7/4 14:26, Brian Becker wrote: > I am booting a kernel with CONFIG_ACPI=n on a platform which does not > support ACPI. Hmmm, so my suggestion is 1. Add quirk to detect 430FX chipset, if detected, disable MSI in this platform. or 2. Append boot argument pci=nomsi in OS command line when the OS running on your old platform. Maybe other guys has some advices. :) > > On Fri, Jul 4, 2014 at 1:59 AM, Yijing Wang <wangyijing at huawei.com> wrote: >>&g...

...generally work for most people :) And it works fine here if MSI is forced off. The problem here is that pci_enable_msi() succeeds, but it probably shouldn't. I don't know all the details about MSI, but doesn't the CPU or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX chipset board. Both quite ancient... So given that the PCI device itself supports MSI, how do we tell that it shouldn't actually get turned on? -ilia > > On 2014/7/4 8:35, Brian Becker wrote: >> I mistakenly only replied to Yijing Wang the first time. Here are the further detai...

...subsystem is missing on > inheriting MSI capabilities somewhere? pci_enable_msi() will checking your device whether it supports MSI. Can you provide the detailed lspci information ? eg. lspci -vvvxxx ? > > -ilia > > [1] > > 00:00.0 Host bridge [0600]: Intel Corporation 430FX - 82437FX TSC > [Triton I] [8086:122d] (rev 01) > Flags: bus master, medium devsel, latency 64 > > 00:0e.0 PCI bridge [0604]: PLX Technology, Inc. PEX8112 x1 Lane PCI > Express-to-PCI Bridge [10b5:8112] (rev aa) (prog-if 00 [Normal > decode]) > Flags: bus maste...

>>> There is a NVIDIA G96 GPU (which is PCIe only) hanging off of a PCIe >>> <-> PCI bridge (all on one card), which is plugged into a motherboard >>> with the 430FX chipset (PCI 2.0 supported). >>> >>> The GPU PCI device, of course, has full support for MSI. However my >>> understanding is that MSI won't actually work here. This is confirmed >>> by the fact that if we let nouveau enable MSI, the device doesn't work &...

...ot;pci=nomsi". But as you say, it's unreasonable to add quirks for all old systems. Brian, can you open a report at http://bugzilla.kernel.org and attach a complete dmesg log, /proc/cpuinfo contents, and "lspci -vvv" output? If I understand correctly, you have a P200MMX with a 430FX chipset. I'm not a hardware guy, but sounds like that might be a 200MHz Pentium with MMX (P54CS), which does have an integrated LAPIC, according to wikipedia. >From the PCI host bridge's perspective, an incoming MSI just looks like a normal DMA write. As long as that write reaches the...

...you say, > it's unreasonable to add quirks for all old systems. > > Brian, can you open a report at http://bugzilla.kernel.org and attach > a complete dmesg log, /proc/cpuinfo contents, and "lspci -vvv" output? > > If I understand correctly, you have a P200MMX with a 430FX chipset. > I'm not a hardware guy, but sounds like that might be a 200MHz Pentium > with MMX (P54CS), which does have an integrated LAPIC, according to > wikipedia. > > From the PCI host bridge's perspective, an incoming MSI just looks > like a normal DMA write. As long a...

...us returns 1, suggesting that it supports MSI. However, this "00:0e.0 PCI bridge: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa)" is a component of the addin card. Wouldn't the lack of support for MSI by the chipset "00:00.0 Host bridge: Intel Corporation 430FX - 82437FX TSC [Triton I] (rev 01)" preclude the use of MSI with buses attached via a bridge? Thanks, Brian On Thu, Jul 3, 2014 at 10:35 PM, Yijing Wang <wangyijing at huawei.com> wrote: > Hi Brian, > From your 01:00.0 VGA compatible controller PCI config register, it supports...

...;use_msi = pci_enable_msi(device->pdev) == 0; Does it need to do more checking than that before trying to enable MSI on the device? Could it be that the linux pci subsystem is missing on inheriting MSI capabilities somewhere? Thanks, -ilia [1] 00:00.0 Host bridge [0600]: Intel Corporation 430FX - 82437FX TSC [Triton I] [8086:122d] (rev 01) Flags: bus master, medium devsel, latency 64 00:0e.0 PCI bridge [0604]: PLX Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge [10b5:8112] (rev aa) (prog-if 00 [Normal decode]) Flags: bus master, 66MHz, medium devsel, latency 66...

...ting > that it supports MSI. However, this "00:0e.0 PCI bridge: PLX > Technology, Inc. PEX8112 x1 Lane PCI Express-to-PCI Bridge (rev aa)" > is a component of the addin card. Wouldn't the lack of support for MSI > by the chipset "00:00.0 Host bridge: Intel Corporation 430FX - 82437FX > TSC [Triton I] (rev 01)" preclude the use of MSI with buses attached > via a bridge? We have no ways to check host bridge whether support MSI routing to CPU, BIOS is responsible for setting and config this in their private registers located in IOH. This is transparent to OS...

I mistakenly only replied to Yijing Wang the first time. Here are the further details. uname -a: Linux p5-133 3.15.2-p5-133 #1 Thu Jun 26 22:56:27 EDT 2014 i586 GNU/Linux Here is the output from lspci -vvvxxx: root at p5-133:~# cat lspci.txt 00:00.0 Host bridge: Intel Corporation 430FX - 82437FX TSC [Triton I] (rev 01) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- Latency: 64 00: 86 80...

...writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR); writel(msg->data, base + PCI_MSIX_ENTRY_DATA); ...... > shouldn't. I don't know all the details about MSI, but doesn't the CPU > or (L)APIC have to support it? In this case, it's a P200MMX on a 430FX > chipset board. Both quite ancient... MSI in x86 always send to specific interrupt address(0xfeexxxx), most x86 CPU should support MSI, but I am not sure, I don't know hardware much. > > So given that the PCI device itself supports MSI, how do we tell that > it shouldn't act...

...eplied to Yijing Wang the first time. Here are the further details. > > uname -a: Linux p5-133 3.15.2-p5-133 #1 Thu Jun 26 22:56:27 EDT 2014 i586 GNU/Linux > > Here is the output from lspci -vvvxxx: > > root at p5-133:~# cat lspci.txt > 00:00.0 Host bridge: Intel Corporation 430FX - 82437FX TSC [Triton I] (rev 01) > Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- > Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR- INTx- > Latenc...