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Displaying 3 results from an estimated 3 matches for "42b9dd40".

2013 Jun 13
0
[LLVMdev] A question w.r.t fence instruction vs. noalias pointer
I mean something like a target-specific fence machine instruction which forces ordering of all loads/stores. I want to clarify the meaning of "noalias" in this case. Is the fence machine instruction considered "touching" all memory and thus breaks the "noalias" contract? Xiaoyi From: Eli Friedman [mailto:eli.friedman at gmail.com] Sent: Wednesday, June 12, 2013 8:08
2013 Jun 13
2
[LLVMdev] A question w.r.t fence instruction vs. noalias pointer
...le-threaded environment, and in a multi-threaded environment it's just a way to express ordering on memory modifications made by other threads. -Eli -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130613/42b9dd40/attachment.html>
2013 Jun 13
2
[LLVMdev] A question w.r.t fence instruction vs. noalias pointer
On Wed, Jun 12, 2013 at 7:28 PM, Guo, Xiaoyi <Xiaoyi.Guo at amd.com> wrote: > So fence only forces ordering of atomic instructions.**** > > ** ** > > Let me change my question then.**** > > ** ** > > If I have a target-specific intrinsic which forces ordering of ordinary > load/store instructions. Then should it also force ordering of load/stores > to