Displaying 18 results from an estimated 18 matches for "416b".
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2016 Dec 22
1
Spill hoisting on RAL: looking for some debugging ideas
Hi,
I am debugging private backend and faced interesting problem:
sometimes spill hoisting creates double stores.
(some output from -debug-only=regalloc).
First hoisting:
Checking redundant spills for 0 at 16r in %vreg19
[16r,144B:0)[144B,240B:1)[240B,280r:2)[296r,416B:3)[416B,456r:4)[472r,592B:5)
0 at 16r 1 at 144B-phi 2 at 240B-phi
3 at 296r 4 at 416B-phi 5 at 472r
Merged to stack int: SS#0 [16r,592B:0) 0 at x
hoisted: 16r STbo %vreg19, <fi#0>
Second below:
Checking redundant spills for 0 at 16r in %vreg19
[16r,96B:0)[144B,240B:1)[296r,416B:2)[416B...
2007 May 16
0
NO ANSWER, When openser make an oubound SIP call to my asterisk
...UDP 192.168.11.9:57536;received=61.217.xxx.xxx
;rport=57536;branch=z9hG4bK834BA777F3C7439EBBC7C4DAECC52FD4.
From: 101 <sip:101@my.openser.domain.name>;tag=3840196923.
To: <sip:0028863939749001@my.openser.domain.name>.
Contact: <sip:101@61.217.xxx.xxx:57536>.
Call-ID: 18875244-8D15-416B-92B7-DD24DA4630E2@192.168.11.9.
CSeq: 4807 INVITE.
Max-Forwards: 69.
Content-Type: application/sdp.
User-Agent: X-LITE build 1082.
Content-Length: 321.
.
v=0.
o=101 45727796 45727796 IN IP4 192.168.11.9.
s=X-LITE.
c=IN IP4 my.openser.ip.addr.
t=0 0.
m=audio 35066 RTP/AVP 0 8 3 18 98 97 101.
a=rtpma...
2020 Nov 11
1
[RFC] A value-tracking LiveDebugValues implementation
...> DBG_VALUE %18:gr32, $noreg, !"15", !DIExpression(), debug-location !50; phi.ll:21:1 line no:21 // Seems still works here. (not "drop the DBG_VALUE ")
> 400B $eax = COPY %17:gr32, debug-location !51; phi.ll:23:1
> 416B RETQ implicit killed $eax, debug-location !51; phi.ll:23:1
> ____________________________________________________
Indeed; it's LiveDebugVariables that drops out-of-liveness DBG_VALUEs,
as seen here:
https://github.com/llvm/llvm-project/blob/68ac02c0dd2b8fda52ac132a86f72f2ad6b139a5/l...
2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...setClass:%5
368B %6:fpuaroutaddregisterclass = HOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5
384B %7:fpuaoffsetclass = COPY %6; FPUaOffsetClass:%7 FPUaROUTADDRegisterClass:%6
400B MOV_A_or killed %7, @c1; FPUaOffsetClass:%7
416B MOV_A_ro @c1, def %8; FPUaOffsetClass:%8
Result: an assertion is raised... !!
********** PROCESS IMPLICIT DEFS **********
********** Function: _start
llc: /home/dte/eclipse-workspace/llvm/lib/CodeGen/MachineRegisterInfo.cpp:366: llvm::MachineInstr* llvm::MachineRegisterInfo::getVRegDef...
2017 May 23
0
classic upgrade, splitting servers
...!
>
> And I still get these problems in the GPO-management.
>
> I translate via googling: "A processing error occurred collecting data
> using this base domain controller."
>
> this one ?
>
> https://social.technet.microsoft.com/Forums/windows/en-US/7dde2a7c-416b-4ba4-8861-cfa915c4eba9/a-processing-error-occurred-collecting-data-using-this-base-domain-controller?forum=winserverGP
That one, what version of windows are you using, 8.8, 8.1 or 10 ?
If you have a win 7 machine, try it from that.
> > In which case, what happened to 'netbios name =...
2017 Nov 01
2
some problem by use libopusenc
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Si...
2017 May 23
3
classic upgrade, splitting servers
...et.
I only did that after sysvolcheck failed!
And I still get these problems in the GPO-management.
I translate via googling: "A processing error occurred collecting data
using this base domain controller."
this one ?
https://social.technet.microsoft.com/Forums/windows/en-US/7dde2a7c-416b-4ba4-8861-cfa915c4eba9/a-processing-error-occurred-collecting-data-using-this-base-domain-controller?forum=winserverGP
but that is NTFS related .... I have to browse all that
>> The smb.conf is quite small ... I used an USB stick now:
>>
>> (from testparm -> )
>
> I ta...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...idx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0
352B %vreg17<def> = LD 32, %vreg1;
mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1
400B %vreg19<def> = LD 40, %vreg0;
mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0
416B %vreg20<def> = LD 40, %vreg1;
mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1
424B %vreg4<def> = DIVD %vreg2, %vreg3;
G8RC:%vreg4,%vreg2,%vreg3
432B %vreg9<def> = DIVD %vreg7, %vreg8;
G8RC:%vreg9,%vreg7,%vreg8
440B...
2017 May 23
2
classic upgrade, splitting servers
Am 2017-05-23 um 19:38 schrieb Rowland Penny:
>> So it sounds like I should raise that level?
>>
>
> You shouldn't need to, lets start with your new DCs smb.conf
set a VM snapshot and raised it already :-P
-
Right now I think I screwed up the default policies somehow
ntacl sysvolreset works
ntacl sysvolcheck ... throws error (hard to paste right now as the
test-LAN is
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...plicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
352B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
368B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
384B $r0 = COPY %1:tgpr
400B $r1 = COPY %1:tgpr
416B $r2 = COPY %0:tgpr
432B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...00_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
register: %vreg49 +[432r,448B:0) phi-join +[448B,496r:1)
BB#1:# derived from
464B%vreg5<...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1)
> 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
> register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1)
> 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
> register: %vreg49 +[432r,448B:0) phi-join +[448B,496r:1)
> BB#1:# derived...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...17 R600_Reg128:%vreg14
336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16
352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17
368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3
384B%T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg2
400B%T1_Z<def> = COPY %vreg1; R600_TReg32:%vreg1
416B%T1_W<def> = COPY %vreg0; R600_TReg32:%vreg0
432BRETURN
# End machine code for function main.
# *** IR Dump Before Local Stack Slot Allocation ***:
# Machine code for function main: SSA
Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1, %T1_Y in %vreg2, %T1_X in %vreg3
Function Live Outs:...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...g16 G8RC_and_G8RC_NOX0:%vreg0
>> 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1
>> 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0
>> 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1
>> 424B %vreg4<def> = DIVD %vreg2, %vreg3; G8RC:%vreg4,%vreg2,%vreg3
>> 432B %vreg9<def> = DIVD %vreg7, %vreg8; G8RC:%vreg9,%vreg7,%vreg...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
> ... Some COPYs....
> 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
> 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
> 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
> Successors according to CFG: BB#1
>
>
> // LOOP CONDITION
> 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%...
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...Successors according to CFG: BB#4
352B BB#4: derived from LLVM BB %while.body
Predecessors according to CFG: BB#4 BB#3
400B %vreg14<def> = LDUBrr %vreg8, 0, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 0)] IntRegs:%vreg14,%vreg8 dbg:../src/getbits.c:56:5
416B STBrr %vreg26, 0, %vreg14<kill>, pred:%noreg; mem:ST1[%p.04] IntRegs:%vreg26,%vreg14 dbg:../src/getbits.c:56:5
432B %vreg27<def> = ADDri %vreg27<kill>, 1, pred:%noreg; IntRegs:%vreg27 dbg:../src/getbits.c:55:5
448B %vreg17<def> = CMPLT_U %vreg27, %vreg6, pred:%noreg; Pred...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
..., so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3
432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13
Successors according to CFG: BB#1
// LOOP CONDITION
464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47
480B%vreg6<d...