Displaying 3 results from an estimated 3 matches for "4150b0d".
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4140b07
2014 Oct 03
1
[PATCH v2 1/2] drm/nouveau/fb/nv50: Add PFB writes
...ield in any changes.
Signed-off-by: Pierre Moreau <pierre.morrow at free.fr>
---
drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
index 4150b0d..5c84d13 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
@@ -289,6 +289,17 @@ nv50_fb_init(struct nouveau_object *object)
if (ret)
return ret;
+ /* Not a clue what this is exactly. Without enabling bit 1 of
+ * 100c14, system wi...
2014 Dec 01
1
Questions about some PFB registers on NVAC cards
...sary. 100c1c and the others hold 32 bits. So are the missing 24 bits of the address forced to zero or do we need to specify them somewhere?
Here is the patch so far, where priv->r100c08 is an address to an empty dma page:
diff --git a/nvkm/subdev/fb/nv50.c b/nvkm/subdev/fb/nv50.c
index 4150b0d..1a0a94e 100644
--- a/nvkm/subdev/fb/nv50.c
+++ b/nvkm/subdev/fb/nv50.c
@@ -295,6 +296,19 @@ nv50_fb_init(struct nouveau_object *object)
*/
nv_wr32(priv, 0x100c08, priv->r100c08 >> 8);
+ /* Enable NISO poller for various clients and set t...
2014 Oct 21
3
Questions about some PFB registers on NVAC cards
(Sending it to the correct Nvidia mailing list, sorry for the spam)
Hi,
When using acceleration with Nouveau on MacBook Pros with an 9400M (NVAC) card,
a PFIFO interrupt 0x00400000 is thrown during the initialisation of that card
(sometime after PFIFO and PGRAPH initialisation) and the laptop will lockup [1],
forcing users to load Nouveau without acceleration.
After some investigation, I found