search for: 414cbd1e3d14

On Sun, 12 May 2019, Halil Pasic wrote: > I've also got code that deals with AIRQ_IV_CACHELINE by turning the > kmem_cache into a dma_pool. > > Cornelia, Sebastian which approach do you prefer: > 1) get rid of cio_dma_pool and AIRQ_IV_CACHELINE, and waste a page per > vector, or > 2) go with the approach taken by the patch below? We only have a couple of users for

On Sun, 12 May 2019, Halil Pasic wrote: > I've also got code that deals with AIRQ_IV_CACHELINE by turning the > kmem_cache into a dma_pool. > > Cornelia, Sebastian which approach do you prefer: > 1) get rid of cio_dma_pool and AIRQ_IV_CACHELINE, and waste a page per > vector, or > 2) go with the approach taken by the patch below? We only have a couple of users for

...change, and ^ 2 > provides the behavior which is closest to the current one. I can see that this is the smallest change on top of the current implementation. I'm good with doing that and looking for further simplification/unification later. > Commit 414cbd1e3d14 "s390/airq: provide cacheline aligned > ivs" (Sebastian Ott, 2019-02-27) could have been smaller had you implemented > 'kmem_cache for everything' (and I would have had just to replace kmem_cache with > dma_cache to achieve option 3). For some reason you decided to keep t...

...l with cachesize > alignment for everything (as a prerequisite we have to limit > config PCI_NR_FUNCTIONS to 2K - but that is not a real constraint). > I prefer option 3 because it is conceptually the smallest change, and provides the behavior which is closest to the current one. Commit 414cbd1e3d14 "s390/airq: provide cacheline aligned ivs" (Sebastian Ott, 2019-02-27) could have been smaller had you implemented 'kmem_cache for everything' (and I would have had just to replace kmem_cache with dma_cache to achieve option 3). For some reason you decided to keep the iv->vecto...