search for: 40b

Yeah, the alternative is to do movabs and then test, which is doable but I’m not sure if it’s worth it (surely BT + risk of flags merging penalty has to be better than two ops, one of which is ~9-10 bytes). Fiona > On Jan 22, 2015, at 2:59 PM, Chris Sears <chris.sears at gmail.com> wrote: > > My bad on that. So that's what the comment meant. > That means BT is pretty much

On Thu Jan 22 2015 at 3:32:53 PM Chris Sears <chris.sears at gmail.com> wrote: > The status quo is: > > a) 40b REX+BT instruction for the 64b case > b) 48b TEST for the 32b case > c) unless it's small TEST > > > You are currently paying a 16b penalty for TEST vs BT in the 32b case. > That may be worth testing the -Os flag. > You'll want -Oz here, Os isn't supposed to affect...

...uot; instructions). The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: 32B %vreg29<def> = LDImm 1; REG1:%vreg29 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143 72B %vreg78<def> = LDImm 32; REG1:%vreg78 But when I specify -g, this becom...

...hu, Jan 22, 2015 at 4:34 PM, Eric Christopher <echristo at gmail.com <mailto:echristo at gmail.com>> wrote: > > > On Thu Jan 22 2015 at 3:32:53 PM Chris Sears <chris.sears at gmail.com <mailto:chris.sears at gmail.com>> wrote: > The status quo is: > > a) 40b REX+BT instruction for the 64b case > b) 48b TEST for the 32b case > c) unless it's small TEST > > You are currently paying a 16b penalty for TEST vs BT in the 32b case. > That may be worth testing the -Os flag. > > You'll want -Oz here, Os isn't supposed to affec...

...Propagation Pass' on function '@d' I dumped the debug during this, and found the following interesting bits: 0B bb.0.entry: liveins: $r4 16B %1:gprc_and_gprc_nor0 = COPY $r4 32B %2:gprc = SPELWZ 0, undef %3:gprc_and_gprc_nor0 :: (load 4 from `float* undef`) 40B %5:gprc = SPELWZ 0, killed %1:gprc_and_gprc_nor0 :: (load 4 from %ir.b1) 48B %4:sperc = COPY killed %2:gprc 80B %6:sperc = COPY killed %5:gprc ... MCP: Copy is a deletion candidate: renamable $s29 = COPY killed renamable $r4 MCP: Copy is used - not dead: renamable $s29 = COPY...

...The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143 > 72B %vreg78<def> = LDImm 32; REG1:%vreg78 > > But when...

...The only difference I can see is the value assigned to the slot index for each instruction. As an example, without -g a snippet of a basic block looks like this: > > 32B %vreg29<def> = LDImm 1; REG1:%vreg29 > 36B %vreg44<def> = LDImm 1103515245; REG1:%vreg44 > 40B %vreg143:vsub32_1<def,read-undef> = LDImm 0; REG2:%vreg143 > 44B %vreg68<def> = LDImm 12345; REG1:%vreg68 > 64B %vreg143:vsub32_0<def> = COPY %vreg143:vsub32_1; REG2:%vreg143 > 72B %vreg78<def> = LDImm 32; REG1:%vreg78 > > But when...

...<3fe> DW_AT_location : 0xa8 (location list) <2><402>: Abbrev Number: 23 (DW_TAG_variable) <403> DW_AT_name : i <405> DW_AT_decl_file : 1 <406> DW_AT_decl_line : 18 <407> DW_AT_type : <0x3f> <40b> DW_AT_location : 0xe1 (location list) <2><40f>: Abbrev Number: 28 (DW_TAG_variable) <410> DW_AT_name : (indirect string, offset: 0xf4): children <414> DW_AT_decl_file : 1 <415> DW_AT_decl_line : 19 <416> DW_AT_type...

...this is probably the *wrong* approach for debug info, which, when it's being used, is used everywhere. Right: if we can afford a `DebugLoc` on `Instruction`, I figure we can afford a couple of pointers on `Function`. But maybe a `SmallVector<..., 1>` is too much? (BTW, it would only be 40B, not 64B, although my math error is probably irrelevant.) I'm happy to defer to conventional wisdom here if anyone wants me to (and TBH, I've only been looking at profiles that include debug info, so maybe `sizeof(Function)` matters with -g0). > Have you considered something like TinyP...

...B %vreg31<def> = LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 <<<<<<<<<<<<<<<< Moved instruction 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, when another instruction is schedu...

Is anyone using the VoiceTronic Openline4 PCI (fxo) card? I am trying to setup Asterisk using a Digium 40B (4 port fxs) and an OpenLine4 (4 port fxo), however I can't find any examples or post that utilize this card. I have my stations (Sayson 390) ringing each other, but haven't had any success ringing out. I have the OpenLine4 loaded and all of the new drivers working good, just don't kn...

...mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 > <<<<<<<<<<<<<<<< Moved instruction > 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 > 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > IntRegs:%vreg37 > > This is not caught at this time...

..... $ 55B: num NA NA NA NA NA NA NA NA NA NA ... $ 56A: num NA NA NA NA NA NA NA NA NA NA ... $ 56B: num NA NA NA NA NA NA NA NA NA NA ... $ 59A: num NA NA NA NA NA NA NA NA NA NA ... $ 59B: num NA NA NA NA NA NA NA NA NA NA ... $ 40A: num NA NA NA NA 2.93 3.38 3.19 3.62 2.55 1.69 ... $ 40B: num NA NA NA NA NA NA NA NA NA NA ... $ 39A: num NA NA NA NA NA NA NA NA NA NA ... $ 39B: num NA NA NA NA NA NA NA NA NA NA ... I want to arrange them like this> row.names 01A 02A...... 1 first value first value 2 second value second value 3 4 .. max(nrow) Thank...

...optimise this edge case where it's in bounds of the granule padding (but not the symbol itself) seems over-the-top. In saying that, it's a possibility for later revisions. > > > The plan calls to > > Realign to granule size (16 bytes), resize to multiple of granule size (e.g. 40B -> 48B). > so this would never happen. > > The symbols are resized in order to prevent smaller untagged symbols from getting into the padding of the 16-byte aligned tagged ones. > I'm not sure if it's desirable to change the symbol size just for this reason. The linker could...

...med from > external to hidden. DSO's linked with -Bsymbolic retain their dynamic > symbol table entries, and thus require no special handling. > > > > > > c) All symbols > > > > Realign to granule size (16 bytes), resize to multiple of granule size > (e.g. 40B -> 48B). > > > > Ban data folding (except where contents and size are same, no tail > merging). > > > > In the loader, ensure writable segments (and possibly .rodata, see next > dot point) are mapped MAP_ANONYMOUS and PROT_MTE (with the contents of the > mappings...

...= LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 <<<<<<<<<<<<<<<< Moved instruction 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, w...

...Driw <fi#-2>, 0; mem:LD4[FixedStack-2] > IntRegs:%vreg31 > 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 > 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 > <<<<<<<<<<<<<<<< Moved instruction > 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 > 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 > 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] > IntRegs:%vreg37 > > This is not caught at this time, and only much later, when anot...

...= LDriw <fi#-2>, 0; mem:LD4[FixedStack-2] IntRegs:%vreg31 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 <<<<<<<<<<<<<<<< Moved instruction 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] IntRegs:%vreg37 This is not caught at this time, and only much later, w...

...ack-2] >> IntRegs:%vreg31 >> 24B %vreg26<def> = COPY %R0<kill>; IntRegs:%vreg26 >> 32B %vreg28<def> = COPY %D1<kill>; DoubleRegs:%vreg28 >> <<<<<<<<<<<<<<<< Moved instruction >> 40B %vreg106<def> = TFRI 16777216; IntRegs:%vreg106 >> 48B %vreg29<def> = COPY %D2<kill>; DoubleRegs:%vreg29 >> 96B %vreg37<def> = LDriw <fi#-8>, 0; mem:LD4[FixedStack-8] >> IntRegs:%vreg37 >> >> This is not caugh...

...den MTE-globals, including those that are transformed from external to hidden. DSO's linked with -Bsymbolic retain their dynamic symbol table entries, and thus require no special handling. c) All symbols 1. Realign to granule size (16 bytes), resize to multiple of granule size (e.g. 40B -> 48B). 2. Ban data folding (except where contents and size are same, no tail merging). 3. In the loader, ensure writable segments (and possibly .rodata, see next dot point) are mapped MAP_ANONYMOUS and PROT_MTE (with the contents of the mappings filled from the file), as...