search for: 400b

...t there becomes two COPYs back to sibling value after the loop. My apologies [vregs 76->111, 87->122]. 1. The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense. selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02 ... queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r queuing new interval:...

...ling value after the loop. My apologies [vregs 76->111, 87->122]. >> >> 1. >> The interval for %vreg111 first covers nearly the entire function. Then it gets split into two intervals, where one covers the inner loops, which makes sense. >> selectOrSplit %vreg111 [68r,400B:1)[400B,688r:6)[688r,752B:4)[752B,1264r:6)[1264r,1312r:3)[1312r,1472B:2)[1472B,1520r:5)[1520r,3488B:0) 0 at 1520r 1 at 68r 2 at 1312r 3 at 1264r 4 at 688r 5 at 1472B-phi 6 at 400B-phi w=3.181050e-02 >> … >> queuing new interval: %vreg121 [1764r,2936r:0)[2960B,2980r:0) 0 at 1764r >&...

...tail-end of the log, with debugging turned on: $llc bugpoint.reduced.simplified.bc -debug ... 208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34 Considering merging to VecRegs with %vreg34 in %vreg13 RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r LHS =...

Hi Quentin, I have tried to find a test case for an official target, but failed. It seems to be a rare case. To do it, I added the 'else' clause in the following: ... if (VNI->def == OrigVNI->def) { DEBUG(dbgs() << "orig phi value\n"); SVI->second.DefByOrigPHI = true; SVI->second.AllDefsAreReloads = false; propagateSiblingValue(SVI); continue;

...ne 1007 (ast_rtp_write): Ooh, format changed from U NKN to ULAW DEBUG[294927]: File channel.c, Line 947 (ast_settimeout): Scheduling timer at 16 0 sample intervals -- Playing 'vm-login' DEBUG[81926]: File chan_sip.c, Line 540 (__sip_ack): Stopping retransmission on '6E5D898E-492D-400B-A42B-8B25FE25F2EE@192.168.7.3' of Response 1: Found DEBUG[294927]: File channel.c, Line 947 (ast_settimeout): Scheduling timer at 0 sample intervals DEBUG[294927]: File channel.c, Line 947 (ast_settimeout): Scheduling timer at 0 sample intervals WARNING[294927]: File app_voicemail2.c, Line 25...

...%18:gr32, implicit-def dead $eflags, debug-location !41; phi.ll:12:1 > DBG_VALUE %18:gr32, $noreg, !"15", !DIExpression(), debug-location !50; phi.ll:21:1 line no:21 // Seems still works here. (not "drop the DBG_VALUE ") > 400B $eax = COPY %17:gr32, debug-location !51; phi.ll:23:1 > 416B RETQ implicit killed $eax, debug-location !51; phi.ll:23:1 > ____________________________________________________ Indeed; it's LiveDebugVariables that drops out-of-liveness DBG_VALUEs, as seen here: https://github....

...5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5 368B %6:fpuaroutaddregisterclass = HOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5 384B %7:fpuaoffsetclass = COPY %6; FPUaOffsetClass:%7 FPUaROUTADDRegisterClass:%6 400B MOV_A_or killed %7, @c1; FPUaOffsetClass:%7 416B MOV_A_ro @c1, def %8; FPUaOffsetClass:%8 Result: an assertion is raised... !! ********** PROCESS IMPLICIT DEFS ********** ********** Function: _start llc: /home/dte/eclipse-workspace/llvm/lib/CodeGen/MachineRegisterInfo.cpp:36...

...can be calculated by dividing the rate by HZ." So, for a 200kbit rate on intel, this would yeld me a minimum burst of 2000bits, or 250 bytes. I then do this: tc qdisc add dev eth0 handle 1: root tbf latency 50ms burst 250b rate 200kbit but all packets are dropped. I then rise burst to 300b, 400b, even 900b and it is still not working. It only starts working when I raise it to 2000b. Which, besides being the wrong unit (bits versus bytes), is the result of the rate/HZ calculation. The tc(8) manpage says that "b or a bare number = bytes", but it seems this parameter ends up being...

...dx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 424B %vreg4<def> = DIVD %vreg2, %vreg3; G...

Hey guys, I am planning to buy some components for a Linux router that will handle the Internet access of 200 computers (includes tc shaping) and some inter sub-network routing (at least 100MBps per eth - and there are 3 eth cards). I was thinking of a: Pentium 4 - 3GHz 256 or 512MB RAM Network Cards. Now - I wonder what is more important: the processor speed or the amount of RAM. And can you

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 352B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 368B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 384B $r0 = COPY %1:tgpr 400B $r1 = COPY %1:tgpr 416B $r2 = COPY %0:tgpr 432B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...

...reg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17 368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3 384B%T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 400B%T1_Z<def> = COPY %vreg1; R600_TReg32:%vreg1 416B%T1_W<def> = COPY %vreg0; R600_TReg32:%vreg0 432BRETURN # End machine code for function main. # *** IR Dump Before Local Stack Slot Allocation ***: # Machine code for function main: SSA Function Live Ins: %T1_W in %vreg0, %T1_Z in %vreg1...

...:0)[880B,1168B:0)  0 at 352r 1 at 336r 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 register: %vreg13 +[368r,432r:0) 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0) 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1) 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1) 432B%vreg49<def> = COPY %vreg13...

...at 336r > 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, > pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 > register: %vreg13 +[368r,432r:0) > 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 > register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0) > 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 > register: %vreg47 +[400r,448B:0) phi-join +[448B,464r:1) > 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 > register: %vreg48 +[416r,448B:0) phi-join +[448B,480r:1) > 432B%vreg49<de...

...g14 G8RC_and_G8RC_NOX0:%vreg1 >> 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 >> 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 >> 400B %vreg19<def> = LD 40, %vreg0; mem:LD8[%arrayidx.5](tbaa=!4) G8RC:%vreg19 G8RC_and_G8RC_NOX0:%vreg0 >> 416B %vreg20<def> = LD 40, %vreg1; mem:LD8[%arrayidx2.5](tbaa=!4) G8RC:%vreg20 G8RC_and_G8RC_NOX0:%vreg1 >> 424B %vreg4<def> = DIVD %v...

...t;BB#5>, pred:%noreg Successors according to CFG: BB#5 304B BB#3: Predecessors according to CFG: BB#2 336B %vreg26<def> = COPY %P0; IntRegs:%vreg26 Successors according to CFG: BB#4 352B BB#4: derived from LLVM BB %while.body Predecessors according to CFG: BB#4 BB#3 400B %vreg14<def> = LDUBrr %vreg8, 0, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32 0)] IntRegs:%vreg14,%vreg8 dbg:../src/getbits.c:56:5 416B STBrr %vreg26, 0, %vreg14<kill>, pred:%noreg; mem:ST1[%p.04] IntRegs:%vreg26,%vreg14 dbg:../src/getbits.c:56:5 432B...

...r if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP > ... Some COPYs.... > 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 > 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 > 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13 > Successors according to CFG: BB#1 > > > // L...

...my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2 416B%vreg48<def> = COPY %vreg3<kill>; R600_Reg128:%vreg48,%vreg3 432B%vreg49<def> = COPY %vreg13<kill>; R600_Reg32:%vreg49,%vreg13    Successors according to CFG: BB#1 // LOOP CONDITION 464B%vreg5<d...