Displaying 2 results from an estimated 2 matches for "4005d5".
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400515
2014 Oct 13
2
[LLVMdev] Unexpected spilling of vector register during lane extraction on some x86_64 targets
...h=native -mtune=native -DSPILLING_ENSUES=0 /* no spilling */
$ objdump -dC --no-show-raw-insn ./a.out
...
00000000004005c0 <main>:
4005c0: movdqa 0x1a58(%rip),%xmm0 # 402020 <x>
4005c8: psrld $0x17,%xmm0
4005cd: paddd 0x12b(%rip),%xmm0 # 400700 <.LCPI0_0>
4005d5: cvtdq2ps %xmm0,%xmm1
4005d8: divps 0x131(%rip),%xmm1 # 400710 <.LCPI0_1>
4005df: cvttps2dq %xmm1,%xmm1
4005e3: pmullw 0x135(%rip),%xmm1 # 400720 <.LCPI0_2>
4005eb: psubd %xmm1,%xmm0
4005ef: movq %xmm0,%rax
4005f4: movslq %eax,%rcx
4005f7: sar $0x20,%r...
2012 May 29
2
[LLVMdev] How to prevent insertion of memcpy()
...-0x8(%rbp)
g_foo = *foo;
4005bc: 48 8b 7d f8 mov -0x8(%rbp),%rdi
4005c0: 64 48 8b 04 25 00 00 mov %fs:0x0,%rax
4005c7: 00 00
4005c9: 48 8d 80 00 f0 ff ff lea -0x1000(%rax),%rax
4005d0: ba 00 10 00 00 mov $0x1000,%edx
4005d5: 48 89 7d f0 mov %rdi,-0x10(%rbp)
4005d9: 48 89 c7 mov %rax,%rdi
4005dc: 48 8b 75 f0 mov -0x10(%rbp),%rsi
4005e0: e8 c3 fe ff ff *callq 4004a8 <memcpy at plt>*
}
4005e5: 48 83 c4 10 add...