Displaying 2 results from an estimated 2 matches for "3f64e2b4".
2010 Jan 04
0
[LLVMdev] ASM output with JIT / codegen barriers
...you care about that, you need to use explicit fencing.
--Owen
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2010 Jan 04
4
[LLVMdev] ASM output with JIT / codegen barriers
In working on an LLVM backend for SBCL (a lisp compiler), there are
certain sequences of code that must be atomic with regards to async
signals. So, for example, on x86, a single SUB on a memory location
should be used, not a load/sub/store sequence. LLVM's IR doesn't
currently have any way to express this kind of constraint (...and
really, that's essentially impossible since