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3e22616c
2013 Nov 22
1
[LLVMdev] prevents instruction-scheduler from interfereing instruction pair
Hi, LLVM list,
I am using Post-RA scheduler to reorder instructions. by now, it's helpful
for our processor but I meet a trouble. In our ISA, we have fixed
instruction pairs. that is to say, our cpu must see instrA right before
instrB. it's not acceptable to have any instruction between them. we call
it an instruction pair.
The problem is I am not aware of describing this kind of