search for: 3e908103

Displaying 3 results from an estimated 3 matches for "3e908103".

2013 Mar 13
2
[LLVMdev] Problems with 64-bit register operands of inline asm on ARM
...%0, %1. > > This is correct. > Ok, so maybe checking all possible ways to require paired registers is not such a bad idea after all. --renato -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130313/3e908103/attachment.html>
2013 Mar 13
0
[LLVMdev] Problems with 64-bit register operands of inline asm on ARM
On Mar 13, 2013, at 10:15 AM, Weiming Zhao <weimingz at codeaurora.org> wrote: > Hi Renato, > > It seems to me that LLVM doesn’t parse the inline asm body. It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1. This is correct. > So it a constraint is a 64-integer type, it *probably*
2013 Mar 13
3
[LLVMdev] Problems with 64-bit register operands of inline asm on ARM
Hi Renato, It seems to me that LLVM doesn’t parse the inline asm body. It just checks the constraints, (ie. Input/output interface). During ASM writing, it then binding those constraints to placeholders like %0, %1. So it a constraint is a 64-integer type, it *probably* needs paired GPR. Weiming Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The