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...MA, ...?). Memcpy implementations > could be a one thing to look at. > This kind of breaks down to how universal you want the memory model to be. Right. For example, the Cray X1 has a much richer set of memory ordering instructions than anything on the commodity micros: http://tinyurl.com/3agjjn The memory ordering intrinsics in the current llvm proposal can't take advantage of them because they are too coarse-grained. Now, I don't expect we'll see an llvm-based X1 code generator, but looking at what the HPC vendors are doing in this area will go a long way toward informin...

...gt; > could be a one thing to look at. > > This kind of breaks down to how universal you want the memory model to be. > > Right. For example, the Cray X1 has a much richer set of memory ordering > instructions than anything on the commodity micros: > > http://tinyurl.com/3agjjn > > The memory ordering intrinsics in the current llvm proposal can't take > advantage of them because they are too coarse-grained. I guess the descriptions on that page are, heh, a little terse ;-). The Cray X1 has a dimension of synchronization that isn't covered in this propo...

...ng to look at. > > > This kind of breaks down to how universal you want the memory model to be. > > > > Right. For example, the Cray X1 has a much richer set of memory ordering > > instructions than anything on the commodity micros: > > > > http://tinyurl.com/3agjjn > > > > The memory ordering intrinsics in the current llvm proposal can't take > > advantage of them because they are too coarse-grained. > > I guess the descriptions on that page are, heh, a little terse ;-). A bit. ;] I was glad to see your clarification. > The &g...

On Thursday 12 July 2007 13:08, Chandler Carruth wrote: > > > Right. For example, the Cray X1 has a much richer set of memory > > > ordering instructions than anything on the commodity micros: > > > > > > http://tinyurl.com/3agjjn > > > > > > The memory ordering intrinsics in the current llvm proposal can't take > > > advantage of them because they are too coarse-grained. > > > > I guess the descriptions on that page are, heh, a little terse ;-). > > A bit. ;] I was glad to se...

Here are some comments, quotes are from the draft. > an operation based constraint cannot guard other operations I think constraints associated with a particular instruction usually apply to this instruction and previous/subsequent instructions, so this wouldn't be true. This is the case in the atomic_ops model, and also on ia64 I think. > The single instruction constraints can,

Hello, This is the second major revision of the atomic proposal for LLVM. I will try and give a brief overview of the motivating changes, but a greater portion of the text has changed, along with some changes to the proposed additions. http://chandlerc.net/llvm_atomics.html - The proposal has been rewritten to better delineate the goals and purposes of LLVM, and these additions to LLVM. The why