search for: 37426prevectorize

...er argument for having the intrinsic is shown in PR37426: https://bugs.llvm.org/show_bug.cgi?id=37426 Vectorization goes overboard because the throughput cost model used by the vectorizers doesn't match the 6 IR instructions that correspond to 1 x86 rotate instruction. Instead, we have: $ opt 37426prevectorize.ll -S -cost-model -analyze ... Cost Model: Found an estimated cost of 1 for instruction: %and = and i32 %cond, 31 Cost Model: Found an estimated cost of 1 for instruction: %shl = shl i32 %1, %and Cost Model: Found an estimated cost of 1 for instruction: %sub = sub nsw i32 0, %cond Cost Model:...

Hi everyone! I recently ran into some interesting issues with generation of rotate instructions - the details are in the bug tracker (https://bugs.llvm.org/show_bug.cgi?id=37387 and related bugs) for those interested - and it brought up the issue of rotates in the IR again. Now this is a proposal that has been made (and been rejected) several times, but I've been told that this time round we