Displaying 9 results from an estimated 9 matches for "368b".
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2018 Sep 10
3
How to avoid multiple registers definitions in customInserter.
...e defined twice
2) %5 is killed twice.
320B MOV_A_ro @a, def %4; FPUaOffsetClass:%4
336B MOV_A_ro @b, def %5; FPUaOffsetClass:%5
352B %6:fpuaroutaddregisterclass = LOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5
368B %6:fpuaroutaddregisterclass = HOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5
384B %7:fpuaoffsetclass = COPY %6; FPUaOffsetClass:%7 FPUaROUTADDRegisterClass:%6
400B MOV_A_or killed %7, @c1; FPUaOffsetClass:%7
416B...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
352B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
368B tBX_RET 14, $noreg
# End machine code for function uECC_shared_secret.
********** SIMPLE REGISTER COALESCING **********
********** Function: uECC_shared_secret
********** JOINING INTERVALS ***********
entry:
16B %2:tgpr = COPY $r2
Considering merging %2 with $r2
Can only merge into reserved r...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...vreg26
register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17
register: %vreg1 replace range with [336r,352r:1) RESULT: [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
register: %vreg13 +[368r,432r:0)
384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
400B%vreg47<def> = COPY %vreg2<kil...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...36r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0)
> 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1
> R600_TReg32:%vreg17
> register: %vreg1 replace range with [336r,352r:1) RESULT:
> [336r,352r:1)[352r,832r:0)[880B,1168B:0) 0 at 352r 1 at 336r
> 368B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1,
> pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
> register: %vreg13 +[368r,432r:0)
> 384B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> register: %vreg0 +[384r,448B:0) +[448B,592B:0) +[880B,1168B:0)
> 400B%vreg47<de...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14
304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2
320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14
336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16
352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17
368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3
384B%T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg2
400B%T1_Z<def> = COPY %vreg1; R600_TReg32:%vreg1
416B%T1_W<def> = COPY %vreg0; R600_TReg32:%vreg0
432BRETURN
# End machine code for function main.
# *** IR Dump Before Local Stack...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...D_SEL_OFF, 0; R600_Reg32:%vreg13
> 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
> 336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12
> Successors according to CFG: BB#1
>
> 352BBB#1: derived from LLVM BB %25
> Predecessors according to CFG: BB#0 BB#3
> 368B%vreg5<def> = PHI %vreg2, <BB#0>, %vreg9, <BB#3>; R600_Reg32:%vreg5,%vreg2,%vreg9
> 384B%vreg6<def> = PHI %vreg3, <BB#0>, %vreg10, <BB#3>; R600_Reg128:%vreg6,%vreg3,%vreg10
> 400B%vreg7<def> = PHI %vreg13, <BB#0>, %vreg11, <BB#3>; R600_Reg3...
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
352B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
368B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
384B $r0 = COPY %1:tgpr
400B $r1 = COPY %1:tgpr
416B $r2 = COPY %0:tgpr
432B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13
320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0
336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12
Successors according to CFG: BB#1
352BBB#1: derived from LLVM BB %25
Predecessors according to CFG: BB#0 BB#3
368B%vreg5<def> = PHI %vreg2, <BB#0>, %vreg9, <BB#3>; R600_Reg32:%vreg5,%vreg2,%vreg9
384B%vreg6<def> = PHI %vreg3, <BB#0>, %vreg10, <BB#3>; R600_Reg128:%vreg6,%vreg3,%vreg10
400B%vreg7<def> = PHI %vreg13, <BB#0>, %vreg11, <BB#3>; R600_Reg32:%vreg7,%...