search for: 344r

...is happening is that although execution reaches to the line spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r >From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 640e %R15R14<def> = COPY %vreg28<kil...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...6.250000e-03 extend $r6 80r-240r i=5.738636e-03 w=6.944444e-03 extend $r6 80r-336r i=5.738636e-03 w=7.440476e-03 (best) extend $r6 80r-432r i=5.738636e-03 all Best local split range: 80r-336r, 1.667770e-03, 4 instrs enterIntvBefore 80r: not live leaveIntvAfter 336r: valno 0 useIntv [80B;344r): [80B;344r):1 blit [80r,432r:0): [80r;344r)=1(%5):0 [344r;432r)=0(%4):0 rewr %bb.0 80r:1 %5:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) rewr %bb.0 144B:1 tBLXr 14, $noreg, %5:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r...

On Nov 30, 2011, at 12:17 PM, Borja Ferrer wrote: > Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): > > for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if

...ng is that although execution reaches to the line spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: > > Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r > From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r > Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 > remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 > 640e %R15R14<def> = COP...

Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg)