Displaying 3 results from an estimated 3 matches for "3403477c".
2011 Aug 25
2
[LLVMdev] AVX spill alignment
Hey guys,
Are spills/reloads of AVX registers using aligned stores/loads? I can't
seem to find the code that aligns the stack slots to 32-bytes. Could
someone point me in the right direction?
Thanks,
Cameron
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2011 Sep 01
0
[LLVMdev] AVX spill alignment
On Aug 25, 2011, at 4:17 PM, Cameron McInally wrote:
> Hey guys,
>
> Are spills/reloads of AVX registers using aligned stores/loads?
Yes.
> I can't
> seem to find the code that aligns the stack slots to 32-bytes. Could
> someone point me in the right direction?
The register class has 256-bit spill alignment:
def VR256 : RegisterClass<"X86", [v32i8, v16i16,
2011 Sep 01
1
[LLVMdev] AVX spill alignment
...6, (sequence "YMM%u", 0, 15)> {
> let SubRegClasses = [(FR32 sub_ss), (FR64 sub_sd), (VR128 sub_xmm)];
> }
>
> /jakob
>
>
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