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Displaying 3 results from an estimated 3 matches for "33fcd17f".

2008 Oct 07
0
[LLVMdev] Multi instruction pattern help
On Oct 6, 2008, at 5:42 PM, Villmow, Micah wrote: > I am trying to get a multi instruction pattern to work and seem to > be running into trouble. > The problem itself is fairly simple. I need to go from 64bit floats > to 32bit integers. As the backend doesn’t support this natively but > has a way of converting it, I’d prefer to get this working via > tablegen. > >
2008 Oct 07
2
[LLVMdev] Multi instruction pattern help
I am trying to get a multi instruction pattern to work and seem to be running into trouble. The problem itself is fairly simple. I need to go from 64bit floats to 32bit integers. As the backend doesn't support this natively but has a way of converting it, I'd prefer to get this working via tablegen. What I thought would work from the previous discussion is the following: def :
2008 Oct 07
3
[LLVMdev] Multi instruction pattern help
...rns an integer type, but it doesn't know which one. Try disambiguating either the input or output with an explicit type, ilke (i32 (fp_to_uint (... -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20081007/33fcd17f/attachment.html>