Displaying 8 results from an estimated 8 matches for "33f".
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2013 Sep 12
2
[LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)
...en bug
> dictate how we implement our functions either).
Looking at the assembly there's something wrong with SI that is not getting saved anywhere after CPUID and 0x20 bit test before it gets overwritten by LEA.
332: mov eax,0x7
337: mov rsi,rbx
33a: cpuid
33c: xchg rsi,rbx
33f: and esi,0x20
342: shr esi,0x5
345: lea rbp,[rip+0x0] # 34c <llvm::sys::getHostCPUName()+0xbc>
34c: lea r12,[rip+0x0] # 353 <llvm::sys::getHostCPUName()+0xc3>
353: cmove rbp,r12
357: lea rdi,[rsp+0x188]
35f: lea rsi,[rip+0x0] # 366 <llvm:...
2013 Sep 13
0
[LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)
...her).
>
> Looking at the assembly there's something wrong with SI that is not
> getting saved anywhere after CPUID and 0x20 bit test before it gets
> overwritten by LEA.
>
> 332: mov eax,0x7
> 337: mov rsi,rbx
> 33a: cpuid
> 33c: xchg rsi,rbx
> 33f: and esi,0x20
> 342: shr esi,0x5
> 345: lea rbp,[rip+0x0] # 34c
> <llvm::sys::getHostCPUName()+0xbc>
> 34c: lea r12,[rip+0x0] # 353
> <llvm::sys::getHostCPUName()+0xc3>
> 353: cmove rbp,r12
> 357: lea rdi,[rsp+0x188]
&g...
2007 Sep 22
2
SPEEX in a DSPIC - optimisation of iir_mem16() for speed - can it be 16 bit ?
Dear Sirs,
I would be interested to hear your views on whether SPEEX could be made to
run fast on a DSPIC33 by the following strategy:
Make iir_mem16() (for example) purely 16 bit by restricting the number of
bits in the signal to say 10 using SATURATE and then making the LPC
co-efficients just 6 bits.
At present (with standard code) the encode function is taking about 140ms
which is seven
2014 Mar 14
1
[Bug 10497] New: rsync fails to sync certain sparse file combinations with compression
...s)", so it appears that the compressed stream is getting corrupted somehow.
strace of the server with 3.1.1pre1 just shows it quitting:
[pid 2216] write(3,
"L\305\254\16_\314\364\307<\207.\355\241#\306\24\274\343\33]1K\274\313(\2560^z\227N\223\350\246\203I\302(\363U!\324\267yVlc\251\33f(-\245\322\306\231n\320\2643\261|\24\324\\(ZV\341\n\21.+\352}\266\236\350\210\303\"I\227\206\360\301\260\263i\222C/\374\360\203\350\200\231\377="...,
504) = 504
[pid 2216] select(1, [0], [], [0], {60, 0}) = 1 (in [0], left {59, 999998})
[pid 2216] read(0,
"\353\202\26\3753\262.8\246...
2013 Sep 13
2
[LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)
...ssembly there's something wrong with SI that is not
>> getting saved anywhere after CPUID and 0x20 bit test before it gets
>> overwritten by LEA.
>>
>> 332: mov eax,0x7
>> 337: mov rsi,rbx
>> 33a: cpuid
>> 33c: xchg rsi,rbx
>> 33f: and esi,0x20
>> 342: shr esi,0x5
>> 345: lea rbp,[rip+0x0] # 34c
>> <llvm::sys::getHostCPUName()+0xbc>
>> 34c: lea r12,[rip+0x0] # 353
>> <llvm::sys::getHostCPUName()+0xc3>
>> 353: cmove rbp,r12
>> 357:...
2013 Sep 12
0
[LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)
Hi Adam,
> OK. I know the reason you cannot reproduce it, before posting
> the patch I've decided to check for AVX before checking AVX2,
> just not to cpuid AVX2 when we don't have AVX1 anyway.
I suspect it was also incompetence on my part. Given the differences
I'm seeing now I can't believe there'd be *no* difference in my tests
if I'd done them properly.
2013 Sep 12
3
[LLVMdev] [PATCH] Detect Haswell subarchitecture (i.e. using -march=native)
> That's far more worrying to me than not being able to detect Haswell.
> I can't reproduce the problem here at the moment: both debug and
> release builds give identical assembly for Host.cpp.
OK. I know the reason you cannot reproduce it, before posting the patch I've decided to check for AVX before checking AVX2, just not to cpuid AVX2 when we don't have AVX1 anyway.
2009 Jul 23
1
[PATCH server] changes required for fedora rawhide inclusion.
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