search for: 336r

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...vm-dev at lists.llvm.org > > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -------------- next part -------------- Computing live-in reg-units in ABI blocks. 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 a...

...rce/ecc_dh.c#L139 Thanks, Prathamesh -------------- next part -------------- PreferIndirect: 1 PreferIndirect: 1 PreferIndirect: 1 Computing live-in reg-units in ABI blocks. 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r %0 [48r,288r:0) 0 at 48r weight:0.000000e+00 %1 [32r,304r:0)...

...e/ew/.maildir/.INBOX.vomiteer/dovecot.index.log", {st_mode=S_IFREG|0600, st_size=26328, ...}) = 0 07:30:17 fstat64(10, {st_mode=S_IFREG|0600, st_size=26328, ...}) = 0 07:30:17 pread64(10, "\200\200\200\207@\0\0\20\0\0\0\0\0\0\0\0$\0\0\0\0\0\0\0\1\0\0\0\200\200\200\214\0\1\0\20\0\0$\0\337!\336R\344\231\2L\0\0\0\0\t\"\336R\t\"\336R\0\0\0\0\t\"\336R\0\0\0\0007\n\0\0\200\200\200\204 \0\0\20@\0\4\0\234e\0\0\200\200\200\242\2\0\0\20\317\0\0\0\10\0\0\0\320\0\0\0\10\0\0\0\321\0\0\0\10\0\0\0\322\0\0\0\10\0\0\0\323\0\0\0\10\0\0\0\324\0\0\0\10\0\0\0\325\0\0\0\10\0\0\0\326\0\0\0\10\0\...

...register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 register: %vreg25 +[208r,272r:0) 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 register: %vreg26 +[224r,336r:0) 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 register: %vr...

...range with [176r,192r:1) RESULT: > [176r,192r:1)[192r,256r:0)  0 at 192r 1 at 176r > 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25 > register: %vreg25 +[208r,272r:0) > 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23 > register: %vreg26 +[224r,336r:0) > 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 > R600_TReg32:%vreg16 > register: %vreg26 replace range with [224r,240r:1) RESULT: > [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r > 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%v...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2

...8:%vreg14 R600_Reg32:%vreg15 register: %vreg14 replace range with [240r,256r:1) RESULT: [240r,256r:1)[256r,320r:0)  0 at 256r 1 at 240r 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 register: %vreg16 +[288r,336r:0) 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y<kill>; R600_Reg32:%vreg17 R600_Reg128:%vreg14 register: %vreg17 +[320r,352r:0) 336B%T2_Z<def> = COPY %vreg16<kill>; R600_Reg32:%vreg16 352B%T2_W<def> = COPY %vreg17<kill&...

https://bugzilla.samba.org/show_bug.cgi?id=5478 Summary: rsync: writefd_unbuffered failed to write 4092 bytes [sender]: Broken pipe (32) Product: rsync Version: 3.0.3 Platform: Other URL: https://bugzilla.samba.org/show_bug.cgi?id=1959 OS/Version: Linux Status: NEW Severity: normal