search for: 336b

...tion !50; phi.ll:21:1 line no:21 > $eax = COPY killed %17:gr32, debug-location !51; phi.ll:23:1 > RETQ implicit killed $eax, debug-location !51; phi.ll:23:1 > ____________________________________________________ > Go on, After Simple Register Coalescing > > 336B bb.3.vaarg.end: > ; predecessors: %bb.2, %bb.1 > > 384B %17:gr32 = ADD32rr %17:gr32(tied-def 0), %18:gr32, implicit-def dead $eflags, debug-location !41; phi.ll:12:1 > DBG_VALUE %18:gr32, $noreg, !"15", !DIExpression(), debug-location !50; phi.ll:21:1...

...My customInserter (see below) is may be over simplistic. After investigation on the code produce by my customInserter, I've noticed the following problems: 1) %6 seems to be defined twice 2) %5 is killed twice. 320B MOV_A_ro @a, def %4; FPUaOffsetClass:%4 336B MOV_A_ro @b, def %5; FPUaOffsetClass:%5 352B %6:fpuaroutaddregisterclass = LOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5 368B %6:fpuaroutaddregisterclass = HOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...cit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %1:tgpr 304B $r1 = COPY %0:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implici...

...dx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 400B %vreg19<def> = LD 40, %vreg0; mem:LD...

...cit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implici...

...12 R600_Reg32:%vreg15 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17 368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3 384B%T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 400B%T1_Z<def> = COPY %vreg1; R600_TReg32:%vreg1 416B%T1_W<def> = COPY...

...g11 G8RC_and_G8RC_NOX0:%vreg1 >> 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 >> 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 >> 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 >> 352B %vreg17<def> = LD 32, %vreg1; mem:LD8[%arrayidx2.4](tbaa=!4) G8RC:%vreg17 G8RC_and_G8RC_NOX0:%vreg1 >> 400B %vreg19<def> = LD 40,...

...:8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\Config.Msi\\3369.rbf"):8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\Config.Msi\\336a.rbf"):8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\Config.Msi\\336b.rbf"):8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\Config.Msi\\336c.rbf"):8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\Config.Msi\\336d.rbf"):8000 attribute(s) not implemented. fixme:file:SetFileAttributesW (L"C:\\C...

...3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 register: %vreg3 +[304r,416r:0) 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28 register: %vreg3 replace range with [304r,320r:1) RESULT: [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26 register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0) 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 R600_TReg32:%vreg17 register: %vreg1 replace range with [336r,352r:1) RESU...

...ill>; R600_Reg128:%vreg3,%vreg27 > register: %vreg3 +[304r,416r:0) > 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 > R600_Reg32:%vreg28 > register: %vreg3 replace range with [304r,320r:1) RESULT: > [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r > 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26 > register: %vreg1 +[336r,448B:0) +[448B,592B:0) +[880B,1168B:0) +[592B,832r:0) > 352B%vreg1:sel_w<def> = COPY %vreg17<kill>; R600_Reg128:%vreg1 > R600_TReg32:%vreg17 > register: %vreg1 replace range wi...

...RUCTION 240B JUMP <BB#3>, pred:%vreg24; PredRegs:%vreg24 Successors according to CFG: BB#6(12) BB#3(20) 256B BB#6: Predecessors according to CFG: BB#2 288B JUMP <BB#5>, pred:%noreg Successors according to CFG: BB#5 304B BB#3: Predecessors according to CFG: BB#2 336B %vreg26<def> = COPY %P0; IntRegs:%vreg26 Successors according to CFG: BB#4 352B BB#4: derived from LLVM BB %while.body Predecessors according to CFG: BB#4 BB#3 400B %vreg14<def> = LDUBrr %vreg8, 0, pred:%noreg; mem:LD1[getelementptr inbounds (%struct.FIFO* @fifo, i32 0, i32...

...1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 > 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 > 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 > 336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12 > Successors according to CFG: BB#1 > > 352BBB#1: derived from LLVM BB %25 > Predecessors according to CFG: BB#0 BB#3 > 368B%vreg5<def> = PHI %vreg2, <BB#0>, %vreg9, <BB#3>; R600_Reg32:%vreg5,%vreg2,%vre...

...reg28 288B%vreg1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12    Successors according to CFG: BB#1 352BBB#1: derived from LLVM BB %25    Predecessors according to CFG: BB#0 BB#3 368B%vreg5<def> = PHI %vreg2, <BB#0>, %vreg9, <BB#3>; R600_Reg32:%vreg5,%vreg2,%vreg9 384B%vreg6<def> =...

https://bugzilla.samba.org/show_bug.cgi?id=5478 Summary: rsync: writefd_unbuffered failed to write 4092 bytes [sender]: Broken pipe (32) Product: rsync Version: 3.0.3 Platform: Other URL: https://bugzilla.samba.org/show_bug.cgi?id=1959 OS/Version: Linux Status: NEW Severity: normal