search for: 320b

...en allocated for the out of the pseudo. So far, so good. My customInserter (see below) is may be over simplistic. After investigation on the code produce by my customInserter, I've noticed the following problems: 1) %6 seems to be defined twice 2) %5 is killed twice. 320B MOV_A_ro @a, def %4; FPUaOffsetClass:%4 336B MOV_A_ro @b, def %5; FPUaOffsetClass:%5 352B %6:fpuaroutaddregisterclass = LOR_A_oo killed %5, implicit-def %rflaga; FPUaROUTADDRegisterClass:%6 FPUaOffsetClass:%5 368B %6:fpuaroutaddregisterclass = HOR_A_oo ki...

...plicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit...

...ter: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 register: %vreg28 +[288r,320r:0) 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 register: %vreg3 +[304r,416r:0) 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28 register: %vreg3 replace range with [304r,320r:1) RESULT: [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26 register: %vreg1 +[336r,448...

...[256r,272r:1) RESULT: > [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r > 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > register: %vreg28 +[288r,320r:0) > 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 > register: %vreg3 +[304r,416r:0) > 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 > R600_Reg32:%vreg28 > register: %vreg3 replace range with [304r,320r:1) RESULT: > [304r,320r:1)[320r,416r:0)  0 at 320r 1 at 304r > 336B%vreg1<def> = COPY %vreg26<kill>; R600_Reg128:%vreg1,%vreg26 >...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

...1\317R}\3341<S\210\274"..., 1024) = 1024 write(5, "\215\34\353\364&\334{\313On~\362\\\271\315V0m\\\315\22"..., 1024) = 1024 write(5, "$\243\n\307I\374\315A\3\34\30\nt[;\223\36r\273O\356\331"..., 1024) = 1024 write(5, "\216\215\266\346+sV\356\223+3\375\355^r\267o\320b I\22"..., 1024) = 1024 write(5, "\372\360S$\365${y!]\3360\17\21\376\257\360\365g\2753XW"..., 1024) = 1024 write(5, "\265\344\216D\344\250e\346\17w9\255/o\253_\246\211\330"..., 1024) = 1024 write(5, "\324\375\242\235e\307\335\312B\334\247\265O^\21!?\221\257"..., 10...

...S\210\274"..., 1024) =3D = 1024 write(5, = "\215\34\353\364&\334{\313On~\362\\\271\315V0m\\\315\22"..., 1024) =3D = 1024 write(5, = "$\243\n\307I\374\315A\3\34\30\nt[;\223\36r\273O\356\331"..., 1024) =3D = 1024 write(5, "\216\215\266\346+sV\356\223+3\375\355^r\267o\320b = I\22"..., 1024) =3D 1024 write(5, = "\372\360S$\365${y!]\3360\17\21\376\257\360\365g\2753XW"..., 1024) =3D = 1024 write(5, = "\265\344\216D\344\250e\346\17w9\255/o\253_\246\211\330"..., 1024) =3D = 1024 write(5, = "\324\375\242\235e\307\335\312B\334\247\265O^\21!?\22...

...plicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %1:tgpr 304B $r1 = COPY %0:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit...

...%vreg28<def> = LI 0; GPRC:%vreg28 272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17 288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30 304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31 320B B <BB#8> Successors according to CFG: BB#8 So maybe LiveInterval would need to be updated to support terminators that define registers? There are also mis-compiles, but I'm hoping that they all stem from the same underlying problem. Thanks again, Hal > > /...

...42 > > And after the pass : > > //Before Loop > ...Some COPYs... > 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 > 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 > 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 > 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 > > //LOOP CONDITION > 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49 > 544B%PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Re...

...> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17 368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg3 384B%T1_Y<def> = COPY %vreg2; R600_TReg32:%vreg...

Some weeks ago, I asked if anyone had set up a backup scheme for a remote server. By backup here, I mean an alternative arrangement that can be called upon if eg the DSL connection to the remote machine fails. I received one interesting reply: ====================== At home, besides my fixed lines, I have two gsm-modems, one low-speed (that came free of charge with one of my fixed lines), the

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the

...COPY %vreg42<kill>; R600_Reg32:%vreg42 And after the pass : //Before Loop ...Some COPYs... 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 //LOOP CONDITION 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49 544B%PREDICATE_BIT<def> = PRED_X %vreg30, 152, 16; R600_Reg32:%vreg30 560BJUM...