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...; --- This should probably be squashed into the GM20B DFS patch to avoid breaking bisecting. Sorry about this. drm/nouveau/nvkm/subdev/clk/gm20b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c index 3089e4bc5e54..4ea89f71cd4f 100644 --- a/drm/nouveau/nvkm/subdev/clk/gm20b.c +++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c @@ -946,11 +946,13 @@ gm20b_clk_init_fused_params(struct gm20b_clk *clk) { struct nvkm_subdev *subdev = &clk->base.base.subdev; u32 val; - u32 rev; + u32 rev = 0; +#if IS_ENABLED(C...

This series adds support for GM20B PLL's Maxwell features, namely glitchless switch and (more importantly) DFS support. DFS lets the PLL lower its output speed according to input current variations, making the clock more stable and allowing it to run safely at lower voltage. All GM20B additions are done in the last patch, which consequently ends up being considerably big ; fortunately, it