Displaying 9 results from an estimated 9 matches for "304r".
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2012 Aug 06
4
[LLVMdev] Register Coalescer does not preserve TargetFlag
...regalloc pass (TF=2 corresponds to a Neg TargetFlag) :
352B %vreg20:sel_x<def,undef> = COPY %vreg16<kill>[TF=2], %vreg20<imp-def>; R600_Reg128:%vreg20 R600_Reg32:%vreg16
Considering merging %vreg16 with %vreg20:sel_x
Cross-class to R600_Reg128.
RHS = %vreg16 = [304r,352r:0) 0 at 304r
LHS = %vreg20 = [352r,400r:0) 0 at 352r
updated: 304B %vreg20:sel_x<def,undef> = MUL %vreg3:sel_x<kill>, %vreg15; R600_Reg128:%vreg20,%vreg3 R600_Reg32:%vreg15
Joined. Result = %vreg20 = [304r,400r:0) 0 at 304r
I'd like to prevent this sp...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...ct: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+00
%1 [32r,304r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0) 0 at 16r weight:0.000000e+00
%3 [80r,336r:0...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...g26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0) 0 at 240r 1 at 224r
256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
register: %vreg27 +[256r,304r:0)
272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25
register: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0) 0 at 272r 1 at 256r
288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
register: %vreg28 +[288r,320r:0)
304B...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg16<kill>; R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> register: %vreg26 replace range with [224r,240r:1) RESULT:
> [224r,240r:1)[240r,336r:0) 0 at 240r 1 at 224r
> 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24
> register: %vreg27 +[256r,304r:0)
> 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27
> R600_Reg32:%vreg25
> register: %vreg27 replace range with [256r,272r:1) RESULT:
> [256r,272r:1)[272r,304r:0) 0 at 272r 1 at 256r
> 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28
> regis...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...art --------------
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 at 128r
%0 [48r,416r:0) 0 at 48r weight:0.000000e+00
%1 [32r,400r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2008 Jun 30
4
Rebuild of kernel 2.6.9-67.0.20.EL failure
Hello list.
I'm trying to rebuild the 2.6.9.67.0.20.EL kernel, but it fails even without
modifications.
How did I try it?
Created a (non-root) build environment (not a mock )
Installed the kernel.scr.rpm and did a
rpmbuild -ba --target=`uname -m` kernel-2.6.spec 2> prep-err.log | tee
prep-out.log
The build failed at the end:
Processing files: kernel-xenU-devel-2.6.9-67.0.20.EL
Checking