search for: 304b

...s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...

...ified by sieve_before and sieve_after As I said, the scripts compile just fine. 8 -rw-r--r-- 1 root wheel 117B Oct 21 12:49 filespam.sieve 8 -rw-r--r-- 1 vmail wheel 256B Oct 21 12:52 filespam.svbin 8 -rw-r--r-- 1 root wheel 137B Oct 21 14:06 bcc.sieve 8 -rw-r--r-- 1 vmail wheel 304B Oct 21 14:10 bcc.svbin > protocol sieve { > mail_plugins = $mail_plugins > mail_max_userip_connections = 10 > managesieve_notify_capability = mailto > managesieve_sieve_capability = fileinto reject envelope encoded-character vacation subaddress comparator-i;ascii-numeric r...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...> = COPY %vreg16<kill>[TF=2], %vreg20<imp-def>; R600_Reg128:%vreg20 R600_Reg32:%vreg16     Considering merging %vreg16 with %vreg20:sel_x     Cross-class to R600_Reg128.         RHS = %vreg16 = [304r,352r:0)  0 at 304r         LHS = %vreg20 = [352r,400r:0)  0 at 352r         updated: 304B    %vreg20:sel_x<def,undef> = MUL %vreg3:sel_x<kill>, %vreg15; R600_Reg128:%vreg20,%vreg3 R600_Reg32:%vreg15     Joined. Result = %vreg20 = [304r,400r:0)  0 at 304r I'd like to prevent this specific join from occuring, because DST register cannot be negated. Is there a way to contr...

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

On 10/21/20 2:12 PM, @lbutlr wrote: > Do I HAVE to have a default.sieve, that's the only thing that I can think the has changed in that folder. RE: compile, fyi note @ https://wiki2.dovecot.org/Pigeonhole/Sieve/Usage#Manually_Compiling_Sieve_Scripts https://wiki2.dovecot.org/Pigeonhole/Sieve/Configuration#Executing_Multiple_Scripts_Sequentially the conditions under which you need to

...s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %1:tgpr 304B $r1 = COPY %0:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...

...is: 240B BB#3: Predecessors according to CFG: BB#2 256B %vreg28<def> = LI 0; GPRC:%vreg28 272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17 288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30 304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31 320B B <BB#8> Successors according to CFG: BB#8 So maybe LiveInterval would need to be updated to support terminators that define registers? There are also mis-compiles, but I'm hoping th...

...PLICIT_DEF; R600_Reg32:%vreg15 256B%vreg14<def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 352B%T2_W<def> = COPY %vreg17; R600_Reg32:%vreg17 368B%T1_X<def> = COPY %vreg3; R600_TReg32:%vreg...

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the

...304r:0) 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 register: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 register: %vreg28 +[288r,320r:0) 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 register: %vreg3 +[304r,416r:0) 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28 register: %vreg3 replace range with [304r,320r:1) RESULT: [304r,320r:1)[320r,416r:0)  0 at 320r 1 at...

...> = COPY %vreg25<kill>; R600_Reg128:%vreg27 > R600_Reg32:%vreg25 > register: %vreg27 replace range with [256r,272r:1) RESULT: > [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r > 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > register: %vreg28 +[288r,320r:0) > 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 > register: %vreg3 +[304r,416r:0) > 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 > R600_Reg32:%vreg28 > register: %vreg3 replace range with [304r,320r:1) RESULT: > [304r,320r:1)[32...

.../src/getbits.c:53:3 <---- THIS IS THE DEAD INSTRUCTION 240B JUMP <BB#3>, pred:%vreg24; PredRegs:%vreg24 Successors according to CFG: BB#6(12) BB#3(20) 256B BB#6: Predecessors according to CFG: BB#2 288B JUMP <BB#5>, pred:%noreg Successors according to CFG: BB#5 304B BB#3: Predecessors according to CFG: BB#2 336B %vreg26<def> = COPY %P0; IntRegs:%vreg26 Successors according to CFG: BB#4 352B BB#4: derived from LLVM BB %while.body Predecessors according to CFG: BB#4 BB#3 400B %vreg14<def> = LDUBrr %vreg8, 0, pred:%noreg; mem:LD1[ge...

...0_Reg32:%vreg28 > 272B%vreg3<def,tied1> = INSERT_SUBREG %vreg27<tied0>, %vreg28<kill>, sel_w; R600_Reg128:%vreg3,%vreg27 R600_Reg32:%vreg28 > 288B%vreg1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 > 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 > 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 > 336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12 > Successors according to CFG: BB#1 > > 352BBB#1: derived...

...COPY %C1_W; R600_Reg32:%vreg28 272B%vreg3<def,tied1> = INSERT_SUBREG %vreg27<tied0>, %vreg28<kill>, sel_w; R600_Reg128:%vreg3,%vreg27 R600_Reg32:%vreg28 288B%vreg1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 336B%vreg12<def> = IMPLICIT_DEF; R600_Reg32:%vreg12    Successors according to CFG: BB#1 352BBB#1: derived from LLVM BB %25    Pre...