Displaying 2 results from an estimated 2 matches for "2ae78df4".
2011 May 27
0
[LLVMdev] Post-RA scheduler and IssueWidth
...urrently depends on it. Catch-22.
>
> -Andy
>
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2011 May 27
2
[LLVMdev] Post-RA scheduler and IssueWidth
Hi,
Can someone tell me if my understanding is right in that post-RA scheduler
currently assumes no limits on a pipeline's issue width? If so, is it by design
or just overlooked? I have a case for, say, 1-issue pipeline when certain
pipeline resource becomes occupied a few clocks after instruction start, but
hazard evaluation is done incorrectly as scheduler advances clock not for every