search for: 288b

...$s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit...

...idx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 352B %vreg17<def> = LD 32, %vreg1; mem:LD...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

...$s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %1:tgpr 304B $r1 = COPY %0:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit...

...CTR8<imp-use,kill> Successors according to CFG: BB#8 BB#10 the preheader is: 240B BB#3: Predecessors according to CFG: BB#2 256B %vreg28<def> = LI 0; GPRC:%vreg28 272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17 288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30 304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31 320B B <BB#8> Successors according to CFG: BB#8 So maybe LiveInterval would need to be updated to s...

...3, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13 240B%vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15 256B%vreg14<def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COPY %vreg16; R600_Reg32:%vreg16 352B%T2_W<def> = CO...

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the

...g10 G8RC_and_G8RC_NOX0:%vreg0 >> 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 >> 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 >> 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 >> 336B %vreg16<def> = LD 32, %vreg0; mem:LD8[%arrayidx.4](tbaa=!4) G8RC:%vreg16 G8RC_and_G8RC_NOX0:%vreg0 >> 352B %vreg17<def> = LD 32,...

...def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 register: %vreg27 +[256r,304r:0) 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 register: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 register: %vreg28 +[288r,320r:0) 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 register: %vreg3 +[304r,416r:0) 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 R600_Reg32:%vreg28 register: %v...

...t;; R600_Reg128:%vreg27,%vreg24 > register: %vreg27 +[256r,304r:0) > 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 > R600_Reg32:%vreg25 > register: %vreg27 replace range with [256r,272r:1) RESULT: > [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r > 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > register: %vreg28 +[288r,320r:0) > 304B%vreg3<def> = COPY %vreg27<kill>; R600_Reg128:%vreg3,%vreg27 > register: %vreg3 +[304r,416r:0) > 320B%vreg3:sel_w<def> = COPY %vreg28<kill>; R600_Reg128:%vreg3 > R600_...

...f> = CMPEQI %vreg6, 0, pred:%noreg; PredRegs:%vreg12 IntRegs:%vreg6 dbg:../src/getbits.c:53:3 <---- THIS IS THE DEAD INSTRUCTION 240B JUMP <BB#3>, pred:%vreg24; PredRegs:%vreg24 Successors according to CFG: BB#6(12) BB#3(20) 256B BB#6: Predecessors according to CFG: BB#2 288B JUMP <BB#5>, pred:%noreg Successors according to CFG: BB#5 304B BB#3: Predecessors according to CFG: BB#2 336B %vreg26<def> = COPY %P0; IntRegs:%vreg26 Successors according to CFG: BB#4 352B BB#4: derived from LLVM BB %while.body Predecessors according to CFG: B...

...lt;tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25 > 256B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > 272B%vreg3<def,tied1> = INSERT_SUBREG %vreg27<tied0>, %vreg28<kill>, sel_w; R600_Reg128:%vreg3,%vreg27 R600_Reg32:%vreg28 > 288B%vreg1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 > 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 > 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0...

...SUBREG %vreg24<tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25 256B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 272B%vreg3<def,tied1> = INSERT_SUBREG %vreg27<tied0>, %vreg28<kill>, sel_w; R600_Reg128:%vreg3,%vreg27 R600_Reg32:%vreg28 288B%vreg1<def,tied1> = INSERT_SUBREG %vreg26<tied0>, %vreg17, sel_w; R600_Reg128:%vreg1,%vreg26 R600_TReg32:%vreg17 304B%vreg13<def> = MOV 1, 0, 0, 0, %ALU_LITERAL_X, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg13 320B%vreg0<def> = COPY %C0_X; R600_Reg32:%vreg0 336B%vreg1...