search for: 27mhz

Hello, We recently reverse engineered PWM-based voltage management but found an odity in the input clock frequency for the PWM controller. It seems like RM is assuming an input clock of 27.648 MHz instead of the actual 27MHz crystal found on the board. I thus have the following questions: - Is it a fixed value hardcoded in RM? (Current way it is done in Nouveau) - Should we use crystal_MHz * 1.024? I could spend some time hooking up my osciloscope to the VR to check if it is a bringup issue but it would not hel...

...LLB sets 02, both use clk from DPLLA * - */ + */ ret = cdv_sb_read(dev, ref_sfr, &ref_value); if (ret) return ret; @@ -646,7 +646,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, * for DP/eDP. When using SSC clock, the ref clk is 100MHz.Otherwise * it will be 27MHz. From the VBIOS code it seems that the pipe A choose * 27MHz for DP/eDP while the Pipe B chooses the 100MHz. - */ + */ if (pipe == 0) refclk = 27000; else @@ -659,7 +659,7 @@ static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc, } drm_mode_debug_printmodeline(adjusted_m...

This patch set nukes all the dummy crtc mode_fixup implementations. (made on top of Daniel topic/drm-misc branch) Carlos Palminha (16): drm: fixes crct set_mode when crtc mode_fixup is null. drm/cirrus: removed optional dummy crtc mode_fixup function. drm/mgag200: removed optional dummy crtc mode_fixup function. drm/udl: removed optional dummy crtc mode_fixup function. drm/gma: removed

This patch set nukes all the dummy crtc mode_fixup implementations. (made on top of Daniel topic/drm-misc branch) Carlos Palminha (16): drm: fixes crct set_mode when crtc mode_fixup is null. drm/cirrus: removed optional dummy crtc mode_fixup function. drm/mgag200: removed optional dummy crtc mode_fixup function. drm/udl: removed optional dummy crtc mode_fixup function. drm/gma: removed