search for: 272b

...dx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 336B %vreg16<def> = LD 32, %vreg0; mem:LD...

...s=sound0.0,cad=0 -device virtio-balloon-pci,id=balloon0,bus=pci.0,addr=0x6 system_u:system_r:svirt_t:s0:c122,c658 qemu 15780 58.4 6.5 3063496 524048 ? Sl 11:47 0:20 /usr/libexec/qemu-kvm -S -M rhel6.2.0 -enable-kvm -m 2048 -smp 4,sockets=4,cores=1,threads=1 -name vm2 -uuid b07607f8-2d03-cc1f-272b-22863667d1a4 -nodefconfig -nodefaults -chardev socket,id=charmonitor,path=/var/lib/libvirt/qemu/vm2.monitor,server,nowait -mon chardev=charmonitor,id=monitor,mode=control -rtc base=utc -no-shutdown -drive file=/var/lib/libvirt/images/vm2.img,if=none,id=drive-virtio-disk0,format=raw,cache=none -devi...

On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote: > 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN > Predecessors according to CFG: BB#0 BB#1 > %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11 > %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12 > %vreg13<def> = BDNZ8 %vreg13,

...z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16 register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 register: %vreg27 +[256r,304r:0) 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 R600_Reg32:%vreg25 register: %vreg27 replace range with [256r,272r:1) RESULT: [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 register: %vreg28 +[288r,320r:0) 304B%vreg3&l...

...ill>; R600_Reg128:%vreg26 > R600_TReg32:%vreg16 > register: %vreg26 replace range with [224r,240r:1) RESULT: > [224r,240r:1)[240r,336r:0)  0 at 240r 1 at 224r > 256B%vreg27<def> = COPY %vreg24<kill>; R600_Reg128:%vreg27,%vreg24 > register: %vreg27 +[256r,304r:0) > 272B%vreg27:sel_z<def> = COPY %vreg25<kill>; R600_Reg128:%vreg27 > R600_Reg32:%vreg25 > register: %vreg27 replace range with [256r,272r:1) RESULT: > [256r,272r:1)[272r,304r:0)  0 at 272r 1 at 256r > 288B%vreg28<def> = COPY %C1_W; R600_Reg32:%vreg28 > register: %vreg28...

...0M sparse image, here's the contents before I've added any files : >> $ ls -lRh a.sparsebundle/ >> total 16 >> -rw-r--r-- 1 simon staff 496B 25 Jan 14:36 Info.bckup >> -rw-r--r-- 1 simon staff 496B 25 Jan 14:36 Info.plist >> drwxr-xr-x 8 simon staff 272B 25 Jan 14:36 bands >> -rw-r--r-- 1 simon staff 0B 25 Jan 14:36 token >> >> a.sparsebundle//bands: >> total 34952 >> -rw-r--r-- 1 simon staff 2.1M 25 Jan 14:37 0 >> -rw-r--r-- 1 simon staff 2.4M 25 Jan 14:36 1 >> -rw-r--r-- 1 simon staff 2....

...4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17...

...ve just created a 100M sparse image, here's the contents before I've added any files : > $ ls -lRh a.sparsebundle/ > total 16 > -rw-r--r-- 1 simon staff 496B 25 Jan 14:36 Info.bckup > -rw-r--r-- 1 simon staff 496B 25 Jan 14:36 Info.plist > drwxr-xr-x 8 simon staff 272B 25 Jan 14:36 bands > -rw-r--r-- 1 simon staff 0B 25 Jan 14:36 token > > a.sparsebundle//bands: > total 34952 > -rw-r--r-- 1 simon staff 2.1M 25 Jan 14:37 0 > -rw-r--r-- 1 simon staff 2.4M 25 Jan 14:36 1 > -rw-r--r-- 1 simon staff 2.0M 25 Jan 14:36 2 > -rw-...

...ording to CFG: BB#8 BB#3 960B BDNZ8 <BB#8>, %CTR8<imp-def>, %CTR8<imp-use,kill> Successors according to CFG: BB#8 BB#10 the preheader is: 240B BB#3: Predecessors according to CFG: BB#2 256B %vreg28<def> = LI 0; GPRC:%vreg28 272B %vreg30<def> = COPY %vreg17<kill>; GPRC:%vreg30,%vreg17 288B %vreg31<def> = RLDICL %vreg30<kill>, 0, 32;GPRC:%vreg31,%vreg30 304B MTCTR8 %vreg31<kill>,%CTR8<imp-def,dead>; GPRC:%vreg31 320B B <BB#8> Su...

...,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13 240B%vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15 256B%vreg14<def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_Reg32:%vreg15 272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3 288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14 304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2 320B%vreg17<def> = COPY %vreg14:sel_y; R600_Reg32:%vreg17 R600_Reg128:%vreg14 336B%T2_Z<def> = COP...

...t; 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 > > And after the pass : > > //Before Loop > ...Some COPYs... > 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 > 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 > 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 > 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 > > //LOOP CONDITION > 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49 &...

Hello again, I am trying to implement an optimization pass for PowerPC such that simple loops use the special "counter register" (CTR) to track the induction variable. This is helpful because, in addition to reducing register pressure, there is a combined decrement-compare-and-branch instruction BZND (there are also other related instructions). I started this process by converting the

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

On Sun, Jan 24, 2016 at 12:29 PM, < dbonde+forum+rsync.lists.samba.org at gmail.com> wrote: > On 2016-01-24 03:51, Kevin Korb wrote: > >> Are you rsyncing from one to the other? Both of them to somewhere >> else? One at a time to somewhere else? Why won't you just show your >> actual command line and an ls -li of the correct source and incorrect >>

...;; R600_Reg32:%vreg42 R600_Reg128:%vreg6 720B%T2_W<def> = COPY %vreg42<kill>; R600_Reg32:%vreg42 And after the pass : //Before Loop ...Some COPYs... 128B%vreg27:sel_x<def,read-undef> = COPY %C1_X; R600_Reg128:%vreg27 192B%vreg27:sel_y<def> = COPY %C1_Y; R600_Reg128:%vreg27 272B%vreg27:sel_z<def> = COPY %C1_Z; R600_Reg128:%vreg27 320B%vreg27:sel_w<def> = COPY %C1_W; R600_Reg128:%vreg27 //LOOP CONDITION 512B%vreg30<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %C0_X, 0, 0, 0, %vreg49, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg30,%vreg49 544B%PREDICATE_BIT&l...

...4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %1:tgpr 304B $r1 = COPY %0:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17...

...eg8 G8RC_and_G8RC_NOX0:%vreg1 >> 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0 >> 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1 >> 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0 >> 288B %vreg14<def> = LD 24, %vreg1; mem:LD8[%arrayidx2.3](tbaa=!4) G8RC:%vreg14 G8RC_and_G8RC_NOX0:%vreg1 >> 336B %vreg16<def> = LD 32,...