Displaying 3 results from an estimated 3 matches for "25e9ba9f".
2010 Sep 08
0
[LLVMdev] Possible missed optimization?
Great analysis Jakob, should this be reported as a missed optimization or
are you going to handle this as you're the register allocator expert here?
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2010 Sep 08
1
[LLVMdev] Possible missed optimization?
...PR with the Thumb1 code. I don't know an easy fix.
/jakob
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2010 Sep 05
2
[LLVMdev] Possible missed optimization?
On Sep 4, 2010, at 5:40 PM, Eli Friedman wrote:
> If you want to take a look at this yourself, the issue is easy to
> reproduce with Thumb1:
Thanks, Eli. Nice catch!
This IR:
target triple = "thumbv5-u-u"
define arm_aapcscc i64 @foo(i64 %a, i64 %b) nounwind readnone {
entry:
%xor = xor i64 %a, 18 ; <i64> [#uses=1]
%xor2 = xor i64 %xor, %b