Displaying 5 results from an estimated 5 matches for "256r".
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2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...g23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15
register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0) 0 at 160r 1 at 144r
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
register: %vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg15<kill>; R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> register: %vreg23 replace range with [144r,160r:1) RESULT:
> [144r,160r:1)[160r,224r:0) 0 at 160r 1 at 144r
> 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
> register: %vreg24 +[176r,256r:0)
> 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
> R600_Reg32:%vreg2
> register: %vreg24 replace range with [176r,192r:1) RESULT:
> [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...[208r,224r:1)[224r,240r:0) 0 at 224r 1 at 208r
240B%vreg14<def> = COPY %vreg12<kill>; R600_Reg128:%vreg14,%vreg12
register: %vreg14 +[240r,320r:0)
256B%vreg14:sel_w<def> = COPY %vreg15<undef>; R600_Reg128:%vreg14 R600_Reg32:%vreg15
register: %vreg14 replace range with [240r,256r:1) RESULT: [240r,256r:1)[256r,320r:0) 0 at 256r 1 at 240r
272B%T2_X<def> = COPY %vreg3; R600_TReg32:%vreg3
288B%vreg16<def> = COPY %vreg14:sel_x; R600_Reg32:%vreg16 R600_Reg128:%vreg14
register: %vreg16 +[288r,336r:0)
304B%T2_Y<def> = COPY %vreg2; R600_TReg32:%vreg2
320B%vreg17&l...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2