search for: 256bits

...AES128+EECDH:AES128+EDH Before I made this change clients were connecting with the following cipher in the log file: ECDHE-ECDSA-AES256-SHA (256/256 bits) After the change the log now says: ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) Is this an improvement (or more secure) despite going from 256bits to 128bits? Thanks!

...p count may not be a multiple of the vector width, and the vectorizer has to execute the last few iterations as scalar code. It keeps a scalar copy of the loop for the remaining iterations. Loop with the large width has a high possibility of executing many scalar iterations. i.e. i8 data type with 256bits target register can vectorize with vector width 32, with that maximum trip count possibility for scalar(epilog) loop is 31, which is significant & worth vectorizing. Large vector factor has following challenges: 1) Possibility of remainder iteration is substantial. 2) Actual trip count...

...2, v4i64, v8f32, v4f64], > 256, (sequence "YMM%u", 0, 15)>; > def VR256X : RegisterClass<"X86", [v32i8, v16i16, v8i32, v4i64, v8f32, v4f64], > 256, (sequence "YMM%u", 0, 31)>; > > Seems to be 256bits/32bytes. Yeah, don't know how I missed that. :) > > I don't know why the alignment was specified the way it is. My guess would be because memory accesses are faster that way (because they do not cross cache lines for example). This is certainly true on older cores, but is actually tr...

...ith the following >> cipher in the log file: >> >> ECDHE-ECDSA-AES256-SHA (256/256 bits) >> >> After the change the log now says: >> >> ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) >> >> Is this an improvement (or more secure) despite going from 256bits to >> 128bits? > > yes it is because AES-GCM is currently the best cipher suite while there > is no point for AES256, if AES128 will fall then it likely affects > AES256 too and according to Brcue Schneier years ago AES128 has even > less problems then AES256 (too lazy for goo...

Looking around today, it appears that TargetRegisterClass and MCRegisterClass only includes a single alignment. This is documented as being the minimum legal alignment, but it appears to often be greater than this in practice. For instance, on x86 the alignment of %ymm0 is listed as 32, not 1. Does anyone know why this is? Additionally, where are these alignments actually defined? I

...th, and the >> vectorizer has to execute the last few iterations as scalar code. It >> keeps a scalar copy of the loop for the remaining iterations. >> Loop with the large width has a high possibility of executing many >> scalar iterations. >> i.e. i8 data type with 256bits target register can vectorize with >> vector width 32, with that maximum trip count possibility for >> scalar(epilog) loop is 31, which is significant & worth vectorizing. >> Large vector factor has following challenges: >> 1)Possibility of remainder iteration is subst...

...his change clients were connecting with the following > cipher in the log file: > > ECDHE-ECDSA-AES256-SHA (256/256 bits) > > After the change the log now says: > > ECDHE-ECDSA-AES128-GCM-SHA256 (128/128 bits) > > Is this an improvement (or more secure) despite going from 256bits to > 128bits? yes it is because AES-GCM is currently the best cipher suite while there is no point for AES256, if AES128 will fall then it likely affects AES256 too and according to Brcue Schneier years ago AES128 has even less problems then AES256 (too lazy for google it again) -----------...

Hi All First the essentials: dovecot --version: 2.2.15 /usr/local/etc/dovecot/conf.d/10-ssl.conf: ssl = required ssl_cert = </usr/local/openssl/certs/mail.domain.com.chained.dovecot.ecdsa.crt ssl_key = </usr/local/openssl/certs/mail.domain.com.ecdsa.key ssl_protocols = !SSLv2 !SSLv3 ssl_cipher_list =

...p count may not be a multiple of the vector width, and the vectorizer has to execute the last few iterations as scalar code. It keeps a scalar copy of the loop for the remaining iterations. Loop with the large width has a high possibility of executing many scalar iterations. i.e. i8 data type with 256bits target register can vectorize with vector width 32, with that maximum trip count possibility for scalar(epilog) loop is 31, which is significant & worth vectorizing. Large vector factor has following challenges: 1) Possibility of remainder iteration is substantial. 2) Actual trip count a...

...e of the vector width, and the vectorizer has to execute the last few iterations as scalar code. It keeps a scalar copy of the loop for the remaining iterations. >> >> Loop with the large width has a high possibility of executing many scalar iterations. >> i.e. i8 data type with 256bits target register can vectorize with vector width 32, with that maximum trip count possibility for scalar(epilog) loop is 31, which is significant & worth vectorizing. >> >> Large vector factor has following challenges: >> 1) Possibility of remainder iteration is substantia...

...000001FFFFFFF (512M used) [ 14.329152] radeon 0000:01:00.0: GTT: 1024M 0x0000000020000000 - 0x000000005FFFFFFF [ 14.329157] Failed to add WC MTRR for [00000000c0000000-00000000cfffffff]; performance may suffer. [ 14.329160] [drm] Detected VRAM RAM=512M, BAR=256M [ 14.329164] [drm] RAM width 256bits DDR [ 14.329285] [TTM] Zone kernel: Available graphics memory: 2015116 kiB [ 14.329289] [TTM] Initializing pool allocator [ 14.329297] [TTM] Initializing DMA pool allocator [ 14.329322] [drm] radeon: 512M of VRAM memory ready [ 14.329326] [drm] radeon: 1024M of GTT memory ready. [ 14.3...