search for: 256b

...{ u32 hdr_size; }; + /** - * struct hsf_load_header - HS firmware load header + * struct gm200_flcn_bl_desc - DMEM bootloader descriptor + * @signature: 16B signature for secure code. 0s if no secure code + * @ctx_dma: DMA context to be used by BL while loading code/data + * @code_dma_base: 256B-aligned Physical FB Address where code is located + * (falcon's $xcbase register) + * @non_sec_code_off: offset from code_dma_base where the non-secure code is + * located. The offset must be multiple of 256 to help perf + * @non_sec_code_size: the size of the nonSecure c...

...Are you suggesting that there is a way to base spill slots off of RSP when the stack size is unknown at compile time? This does bring up an interesting idea though. If we wanted to punt, it would be possible to check for variable sized objects on the stack and then only issue unaligned moves for 256b spills/reloads. Not ideal for performance, but it would work as a stopgap. -Cameron -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120302/b604f045/attachment.html>

...t in LLVM 2.8? I gather from the release notes that the MC assembler supports it, and clang added support for it. Does clang support mean intrinsics only, or is there support for lowering of some sort of gcc vector extension? If I generate llvm vector instructions, is there support to emit 128 or 256b AVX instructions assuming I run the jit on appropriate sandy bridge hardware? Thanks Bill

...turned into / remain as dynamic allocas OR another register is needed to replace %rsp/%esp in the above. > This does bring up an interesting idea though. If we wanted to punt, it > would be possible to check for variable sized objects on the stack and then > only issue unaligned moves for 256b spills/reloads. Not ideal for > performance, but it would work as a stopgap. The problem is worse on x86-32 following the original sysv ABI. In that case both GCC and LLVM currently just create broken code if a function uses both SSE instructions and alloca. Joerg

...d Predecessors according to CFG: BB#1 224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any pointer") IntRegs:%vreg7,%vreg1 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 256B JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,undef> Hexagon MI scheduler is working with BB1 and picks this load: %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] IntRegs:%vreg10,%vreg9 To be scheduled first (!). Right there after 7 clang...

Add support for XDP adjust head by allocating a 256B header region that XDP programs can grow into. This is only enabled when a XDP program is loaded. In order to ensure that we do not have to unwind queue headroom push queue setup below bpf_prog_add. It reads better to do a prog ref unwind vs another queue setup call. TBD merge with Jason Wang'...

Add support for XDP adjust head by allocating a 256B header region that XDP programs can grow into. This is only enabled when a XDP program is loaded. In order to ensure that we do not have to unwind queue headroom push queue setup below bpf_prog_add. It reads better to do a prog ref unwind vs another queue setup call. TBD merge with Jason Wang'...

...28 DEBUG[4481]: Echo cancellation already on Jan 26 08:45:28 DEBUG[5033]: Dropping duplicate answer! Jan 26 08:45:28 VERBOSE[5033]: !! Unknown IE 124 (cs5, Unknown Information Element) -- Zap/1-1 answered SIP/acasanova-cc59 Jan 26 08:45:28 DEBUG[4475]: Stopping retransmission on '868C81E6-256B-4415-B1C7-F378CA626133@192.168.1.212' of Respons e 1: Found Jan 26 08:45:37 VERBOSE[4481]: == Primary D-Channel on span 1 down Jan 26 08:45:37 DEBUG[5033]: Bridge stops because we're zombie or need a soft hangup: c0=SIP/acasanova-cc59, c1=Zap/1-1 , flags: No,No,No,Yes Jan 26 08:45:37 DEB...

...cording to CFG: BB#1 > 224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any > pointer") IntRegs:%vreg7,%vreg1 > 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>; > mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7 > 256B JMPR %PC<imp-def>, %R31<imp-use>, %R0<imp-use,undef> > > Hexagon MI scheduler is working with BB1 and picks this load: > > %vreg10<def> = LDriw %vreg9<kill>, 0; mem:LD4[%stack.0.in] > IntRegs:%vreg10,%vreg9 > > To be scheduled first (!). Rig...

...this is a simple loop of all function permutations from all procs to all others, but even as you only commit to handling c/c++ currently there is concern that all options are covered. I personally use a library of variable bit length value managers to handle 8bit processors when needed, along with 256b on the 32b ia frequently, so having number scope requirements and verified resolutions optimized in the library to all host machines is critical. To make it short... Are all formats of asm from conventional decompilers read coherently AND THEIR NATIVE OPTIMIZATIONS retained in your modeling data,...

...uting_Multiple_Scripts_Sequentially > > the conditions under which you need to manually pre-compile the scripts specified by sieve_before and sieve_after As I said, the scripts compile just fine. 8 -rw-r--r-- 1 root wheel 117B Oct 21 12:49 filespam.sieve 8 -rw-r--r-- 1 vmail wheel 256B Oct 21 12:52 filespam.svbin 8 -rw-r--r-- 1 root wheel 137B Oct 21 14:06 bcc.sieve 8 -rw-r--r-- 1 vmail wheel 304B Oct 21 14:10 bcc.svbin > protocol sieve { > mail_plugins = $mail_plugins > mail_max_userip_connections = 10 > managesieve_notify_capability = mailto >...

Cameron, Figure 3.3 on page 16 of www.x86-64.org/documentation/abi.pdf is not normative. See foot note 7 in the same page. Figure 3.4 on page 21 confirms that the use of a frame-pointer is optional. So, if one doesn't use ENTER in the prologue and uses RSP to access local variables, RBP may be used as a calee-saved GPR. -- Evandro Menezes Austin, TX emenezes at

...4, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 256B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 272B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 288B $r0 = COPY %0:tgpr 304B $r1 = COPY %1:tgpr 320B $r2 = COPY %2:tgpr 336B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12...

On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote: > Looking at VLIWPacketizerList::PacketizeMIs, it seems like the > instructions are first scheduled (via some external scheme?), and then > packetized 'in order'. Is that correct? Anshu? > In the PowerPC grouping scheme, resources are assigned on a group > basis (by the instruction dispatching

> > At least for 32bit x86 reserving another register as alternative frame > pointer is very heavy. The above would allow normal spill logic to > decide when to keep a reference in register and when not. It also reuses > existing functionality as much as possible. > Hi Joerg, Yes, this was a problem in my implementation also. Empirically, for the chips I work on, reserving the

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

...s0 /dev/dsk/c6t6006016062231B00E2F7A4DA17D9DB11d0s0 /dev/dsk/c6t6006016062231B00DCEA12D017D9DB11d0s0 /dev/dsk/c6t6006016062231B003C3032C517D9DB11d0s0 /dev/dsk/c6t6006016062231B00C497C0AB17D9DB11d0s0 /dev/dsk/c6t6006016062231B001A70C49C17D9DB11d0s0 /dev/dsk/c6t6006016062231B000ABBBE8517D9DB11d0s0 -i 256b bash-3.00# This message posted from opensolaris.org

Even if you explicitly specify –stack-alignment=16 the aligned movs are still generated. It is not an issue related to ABI. See my original mail: ./llc -mattr=+avx -stack-alignment=16 < basic.ll | grep movaps | grep ymm | grep rbp vmovaps -176(%rbp), %ymm14 vmovaps -144(%rbp), %ymm11 vmovaps -240(%rbp), %ymm13 - Elena From: Cameron McInally

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the