Displaying 10 results from an estimated 10 matches for "240r".
Did you mean:
240
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...aster/lib/source/ecc_dh.c#L139
Thanks,
Prathamesh
-------------- next part --------------
PreferIndirect: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+00
%1...
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...> > llvm-dev at lists.llvm.org
> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
-------------- next part --------------
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r...
2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
...; }
Here's the tail-end of the log, with debugging turned on:
$llc bugpoint.reduced.simplified.bc -debug
...
208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34
Considering merging to VecRegs with %vreg34 in %vreg13
RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...rect to me :
********** COMPUTING LIVE INTERVALS **********
********** Function: main
BB#0:# derived from
16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
register: %vreg17 +[16r,352r:0)
32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
register: %vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...TING LIVE INTERVALS **********
> ********** Function: main
> BB#0:# derived from
> 16B%vreg17<def> = COPY %T1_W<kill>; R600_TReg32:%vreg17
> register: %vreg17 +[16r,352r:0)
> 32B%vreg16<def> = COPY %T1_Z<kill>; R600_TReg32:%vreg16
> register: %vreg16 +[32r,240r:0)
> 48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %v...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...vreg11:sel_y<def> = COPY %vreg8<kill>; R600_Reg128:%vreg11 R600_Reg32:%vreg8
register: %vreg11 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,208r:0) 0 at 192r 1 at 176r
208B%vreg12<def> = COPY %vreg11<kill>; R600_Reg128:%vreg12,%vreg11
register: %vreg12 +[208r,240r:0)
224B%vreg12:sel_z<def> = COPY %vreg13<undef>; R600_Reg128:%vreg12 R600_Reg32:%vreg13
register: %vreg12 replace range with [208r,224r:1) RESULT: [208r,224r:1)[224r,240r:0) 0 at 224r 1 at 208r
240B%vreg14<def> = COPY %vreg12<kill>; R600_Reg128:%vreg14,%vreg12
register: %vr...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2008 May 21
35
DO NOT REPLY [Bug 5478] New: rsync: writefd_unbuffered failed to write 4092 bytes [sender]: Broken pipe (32)
https://bugzilla.samba.org/show_bug.cgi?id=5478
Summary: rsync: writefd_unbuffered failed to write 4092 bytes
[sender]: Broken pipe (32)
Product: rsync
Version: 3.0.3
Platform: Other
URL: https://bugzilla.samba.org/show_bug.cgi?id=1959
OS/Version: Linux
Status: NEW
Severity: normal