search for: 224r

...er().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r >From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 640e %R15R14<def> = COPY %vreg28<kill>; DLDREGS:%vreg28 interval: %vreg28,inf = [632r,640r:0)...

...C1_Y; R600_Reg32:%vreg2 register: %vreg2 +[112r,400r:0) 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 register: %vreg21 +[128r,176r:0) 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 register: %vreg23 +[144r,224r:0) 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 register: %vr...

...gister: %vreg2 +[112r,400r:0) > 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; > R600_Reg128:%vreg21 R600_Reg32:%vreg18 > register: %vreg21 +[128r,176r:0) > 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 > register: %vreg23 +[144r,224r:0) > 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 > R600_TReg32:%vreg15 > register: %vreg23 replace range with [144r,160r:1) RESULT: > [144r,160r:1)[160r,224r:0)  0 at 160r 1 at 144r > 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%v...

On Nov 30, 2011, at 12:17 PM, Borja Ferrer wrote: > Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): > > for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; > ++I) > { > unsigned VirtReg = I->first; > if

...LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm getting to show what I mean: > > Inline spilling DLDREGS:%vreg25,1.436782e-03 = [344r,640r:0) 0 at 344r > From original %vreg8,1.838235e-03 = [224r,640r:0) 0 at 224r > Value %vreg25:0 at 344r may remat from %vreg25<def> = LDIWRdK 2; DLDREGS:%vreg25 > remat: 632r %vreg28<def> = LDIWRdK 2; DLDREGS:%vreg28 > 640e %R15R14<def> = COPY %vreg28<kill>; DLDREGS:%vreg28 > interval: %vreg28,...

Thanks for all the hints Jakob, I've added the following piece of code after the spill code handling inside selectOrSplit() (ignoring some control logic): for (LiveIntervals::const_iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { unsigned VirtReg = I->first; if ((TargetRegisterInfo::isVirtualRegister(VirtReg)) && (VRM->getPhys(VirtReg)

...[176r,192r:1)[192r,208r:0)  0 at 192r 1 at 176r 208B%vreg12<def> = COPY %vreg11<kill>; R600_Reg128:%vreg12,%vreg11 register: %vreg12 +[208r,240r:0) 224B%vreg12:sel_z<def> = COPY %vreg13<undef>; R600_Reg128:%vreg12 R600_Reg32:%vreg13 register: %vreg12 replace range with [208r,224r:1) RESULT: [208r,224r:1)[224r,240r:0)  0 at 224r 1 at 208r 240B%vreg14<def> = COPY %vreg12<kill>; R600_Reg128:%vreg14,%vreg12 register: %vreg14 +[240r,320r:0) 256B%vreg14:sel_w<def> = COPY %vreg15<undef>; R600_Reg128:%vreg14 R600_Reg32:%vreg15 register: %vreg14 replace range...

.... 0B %bb.0 R0#0 R1#0 R2#0 Created 3 new intervals. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r %0 [48r,288r:0) 0 at 48r weight:0.000000e+00 %1 [32r,304r:0) 0 at 32r weight:0.000000e+00 %2 [16r,320r:0) 0 at 16r weight:0.000000e+00 %3 [80r,336r:0) 0 at 80r weight:0.000000e+00 RegMasks: 144r 240r 336r ********** MACHINEINSTRS *...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...als. ********** INTERVALS ********** R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 at 128r %0 [48r,416r:0) 0 at 48r weight:0.000000e+00 %1 [32r,400r:0) 0 at 32r weight:0.000000e+00 %2 [16r,320r:0) 0 at 16r weight:0.000000e+00 %3 [80r,432r:0) 0 at 80r weight:0.000000e+00 RegMasks: 144r 240r 336r 432...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2

...00`v?S\035\t\b,g\022\bLw?HF\037\b8]\037\b\020w?f\"\t\b\001\000\000\000=m\022\b\002\000\000\000HF\037\bdw?HF\037\b\030w?+\002\020\b`\215\031\b \000\000\000\004\000\000\000<w?_\031\t\b~g\022\b`\215\031\b \000\000\000R\031\024\b"... filename = "questionnaire_marketsurvey.doc\000\000\224r?(\000\017\b\000\000\000\000`\013\026\b`\021\025@\000\000\000\000Hr? \000\000\000\000\000\000\000\024s?\000\000\000\000\024s?)i\005@\000\000\000\000Pr?}\000\017\b\e\000\000\000\024s?\001\000\000\000`r?(\000\017\b\037]\024\b`\013\026\btr?7\001\017\b\024s?dw?HF\037\b\024w?X\002\017\b\024s?\024s?\003\0...