Displaying 20 results from an estimated 20 matches for "224b".
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2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
192B JMP <BB#2>
Successors according to CFG: BB#2 BB#1
208B BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
pointer") IntRegs:%vreg7,%vreg1
240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7
256B JMPR %PC<imp-def>, %R31<imp-use&g...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...g6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> 192B JMP <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> 208B BB#2: derived from LLVM BB %for.end
> Predecessors according to CFG: BB#1
> 224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
> pointer") IntRegs:%vreg7,%vreg1
> 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
> mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7
> 256B JMPR %PC<imp-def>...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...plicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %1:tgpr
224B $r2 = COPY %2:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...rayidx.1](tbaa=!4)
G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4)
G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
224B %vreg11<def> = LD 16, %vreg1;
mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1
272B %vreg13<def> = LD 24, %vreg0;
mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0
288B %vreg14<def> = LD 24, %vreg1;
mem:LD...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2019 Mar 28
1
Panic: file mail-transaction-log-file.c: line 105 (mail_transaction_log_file_free): assertion failed: (!file->locked)
On 28 Mar 2019, at 10.15, Arkadiusz Mi?kiewicz <arekm at maven.pl> wrote:
>
> error = 0x55e3e2b40ac0 "Fixed index file
> /var/mail/piast_efaktury/dovecot.index: log_file_seq 13 -> 15",
> nodiskspace = true,
This was one of the things I was first wondering, but I'm not sure why it's not logging an error. Anyway, you're using filesystem quota? And this
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...plicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %2:tgpr
224B $r2 = COPY %1:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...RT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6
192B%vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8
208B%vreg13<def> = IMPLICIT_DEF; R600_Reg32:%vreg13
224B%vreg12<def,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13
240B%vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15
256B%vreg14<def,tied1> = INSERT_SUBREG %vreg12<tied0>, %vreg15, sel_w; R600_Reg128:%vreg14,%vreg12 R600_...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> > 192B JMP <BB#2>
> > Successors according to CFG: BB#2 BB#1
> >
> > 208B BB#2: derived from LLVM BB %for.end
> > Predecessors according to CFG: BB#1
> > 224B %vreg7<def> = LDriw %vreg1<kill>, 0;
> mem:LD4[%first1](tbaa=!"any
> > pointer") IntRegs:%vreg7,%vreg1
> > 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
> > mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%vreg7
> > 256B...
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700
Andrew Trick <atrick at apple.com> wrote:
> On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> > I'm considering writing more-detailed itineraries for some PowerPC
> > CPUs that use the 'traditional' instruction grouping scheme. In
> > essence, this means that multiple instructions will stall
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...;BB#1>, %PC<imp-def>;
> PredRegs:%vreg6
> > > 192B JMP <BB#2>
> > > Successors according to CFG: BB#2 BB#1
> > >
> > > 208B BB#2: derived from LLVM BB %for.end
> > > Predecessors according to CFG: BB#1
> > > 224B %vreg7<def> = LDriw %vreg1<kill>, 0;
> > mem:LD4[%first1](tbaa=!"any
> > > pointer") IntRegs:%vreg7,%vreg1
> > > 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
> > > mem:ST4[@yy_instr](tbaa=!"any pointer") IntRegs:%v...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...%vreg7 G8RC_and_G8RC_NOX0:%vreg0
>> 160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
>> 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
>> 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1
>> 272B %vreg13<def> = LD 24, %vreg0; mem:LD8[%arrayidx.3](tbaa=!4) G8RC:%vreg13 G8RC_and_G8RC_NOX0:%vreg0
>> 288B %vreg14<def> = LD 24,...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r:0) 0 at 240...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...4:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
> R600_Reg32:%vreg2
> register: %vreg24 replace range with [176r,192r:1) RESULT:
> [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +[208r,272r:0)
> 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
> register: %vreg26 +[224r,336r:0)
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> register: %vreg26 replace range with [224r,240r:1) RESULT:
> [224r,240...
2012 Sep 18
2
[LLVMdev] liveness assertion problem in llc
...cording to CFG: BB#5
176B BB#2: derived from LLVM BB %while.cond.preheader
Predecessors according to CFG: BB#0
192B %vreg27<def> = MOV32ri 0, pred:%noreg; IntRegs:%vreg27
208B %vreg24<def> = CMPNEI %vreg6, 0, pred:%noreg; PredRegs:%vreg24 IntRegs:%vreg6 dbg:../src/getbits.c:53:3
224B %vreg12<def> = CMPEQI %vreg6, 0, pred:%noreg; PredRegs:%vreg12 IntRegs:%vreg6 dbg:../src/getbits.c:53:3 <---- THIS IS THE DEAD INSTRUCTION
240B JUMP <BB#3>, pred:%vreg24; PredRegs:%vreg24
Successors according to CFG: BB#6(12) BB#3(20)
256B BB#6:
Predecessors accordin...
2020 Jun 26
2
How to implement load/store for vector predicate register
Hi,
I am planning to expanding the pseudo instructions in XXXTargetLowering::EmitInstrWithCustomInserter(), and use temporary virtual registers as operands.
If I use virtual registers, do I need to mark them as "early clobber"?
I saw that sometimes they marked virtual register as "early clobber" in EmitInstrWithCustomInserter() in MIPS backend.
What is the effect of marking a
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
> 192B%vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> 224B%vreg26<def,tied1> = INSERT_SUBREG %vreg23<tied0>, %vreg16, sel_z; R600_Reg128:%vreg26,%vreg23 R600_TReg32:%vreg16
> 240B%vreg27<def,tied1> = INSERT_SUBREG %vreg24<tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25
> 256B%vreg28<def>...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15
192B%vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
224B%vreg26<def,tied1> = INSERT_SUBREG %vreg23<tied0>, %vreg16, sel_z; R600_Reg128:%vreg26,%vreg23 R600_TReg32:%vreg16
240B%vreg27<def,tied1> = INSERT_SUBREG %vreg24<tied0>, %vreg25<kill>, sel_z; R600_Reg128:%vreg27,%vreg24 R600_Reg32:%vreg25
256B%vreg28<def> = COPY %...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...se
Predecessors according to CFG: BB#0
176B %vreg2<def> = MOVri 0; GPRegs:%vreg2
192B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
Successors according to CFG: BB#3
208B BB#3: derived from LLVM BB %return
Predecessors according to CFG: BB#2 BB#1
224B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
240B %R2<def> = COPY %vreg4; GPRegs:%vreg4
256B RET
# End machine code for function isZero.
********** Stack Coloring **********
********** Function: isZero
Found 0 markers and 2 slots
Slot structure:
Slot #0 - 4...