Displaying 1 result from an estimated 1 matches for "21b80342".
2014 Dec 24
2
[LLVMdev] Generating code for target with immediate constant?
To generate code for a target which doesn't have immediate constant as
instruction operand, do I (the target specific back-end, XXXTarget) need to
provide code to break up the SDNode with constant (like ISD::ADD $reg1, #1)
to 2 SDNodes (ISD::LOAD $reg2, #1; ISD::ADD $reg1, $reg2) in my
XXXTargetLowering::LowerOperation, or LLVM target-independent framework can
do such transformation