Displaying 9 results from an estimated 9 matches for "208r".
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2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
...672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384B:1)[400B,672r:1) 0 at x 1 at 240r L00000010 [160r,384B:1)[400B,672r:1) 0 at x 1 at 160r L00000002 [480r,480d:1)[496r,672r:0) 0 at 496r 1 at 480r L00000001 [480r,672r:0) 0 at 480r
LHS = %vreg13 [96r,112r:0)[112r,208r:1)[208r,288r:2) 0 at 96r 1 at 112r 2 at 208r L00000002 [96r,96d:1)[112r,288r:0) 0 at 112r 1 at 96r L00000030 [208r,288r:1) 0 at x 1 at 208r L00000001 [96r,288r:0) 0 at 96r
merge %vreg13:2 at 208r into %vreg34:0 at 160r --> @160r
LHST = %vreg13 %vreg13 [96r,112...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...600_Reg32:%vreg8,%vreg7,%vreg5
register: %vreg8 +[144r,192r:0)
160B%vreg9:sel_x<def,read-undef> = COPY %vreg6<kill>; R600_Reg128:%vreg9 R600_Reg32:%vreg6
register: %vreg9 +[160r,176r:0)
176B%vreg11<def> = COPY %vreg9<kill>; R600_Reg128:%vreg11,%vreg9
register: %vreg11 +[176r,208r:0)
192B%vreg11:sel_y<def> = COPY %vreg8<kill>; R600_Reg128:%vreg11 R600_Reg32:%vreg8
register: %vreg11 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,208r:0) 0 at 192r 1 at 176r
208B%vreg12<def> = COPY %vreg11<kill>; R600_Reg128:%vreg12,%vreg11
register: %vreg1...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...PreferIndirect: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+00
%1 [32r,304r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0) 0 at 16r weight:0.000000e+00
%...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...------ next part --------------
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 at 128r
%0 [48r,416r:0) 0 at 48r weight:0.000000e+00
%1 [32r,400r:0) 0 at 32r weight:0.000000e+00
%...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...1
register: %vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
register: %vreg26 replace range with [224r,240r:1) RESULT: [224r,240r:1)[240r,336r...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...0)
> 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
> R600_Reg32:%vreg2
> register: %vreg24 replace range with [176r,192r:1) RESULT:
> [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +[208r,272r:0)
> 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
> register: %vreg26 +[224r,336r:0)
> 240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26
> R600_TReg32:%vreg16
> register: %vreg26 replace range with [224r,240r:1) RESUL...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2