Displaying 20 results from an estimated 26 matches for "208b".
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2017 Sep 26
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...in his out-of-tree target
with the MachineCopyPropagation changes to forward registers (which is
currently reverted). The verification in question is:
*** Bad machine code: Multiple connected components in live interval ***
- function: utils_la_suite_matmul_ref
- interval: %vreg77
[192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi
2 at 312r 3 at 380r
0: valnos 0 1 3
1: valnos 2
In this particular case, I believe that it is the greedy allocator that
is creating the multiple components in the %vreg77 live interval. If
you look at the attached debug dump fi...
2017 Sep 26
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...ee target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is:
>
> *** Bad machine code: Multiple connected components in live interval ***
> - function: utils_la_suite_matmul_ref
> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
> 0: valnos 0 1 3
> 1: valnos 2
>
> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 live interval. If you look at the attac...
2017 Sep 26
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is:
>>
>> *** Bad machine code: Multiple connected components in live interval ***
>> - function: utils_la_suite_matmul_ref
>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>> 0: valnos 0 1 3
>> 1: valnos 2
>>
>> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 live interval. If you lo...
2017 Sep 26
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...opagation changes to forward registers (which is currently reverted). The verification in question is:
>>>
>>> *** Bad machine code: Multiple connected components in live interval ***
>>> - function: utils_la_suite_matmul_ref
>>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>>> 0: valnos 0 1 3
>>> 1: valnos 2
>>>
>>> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 live int...
2017 Sep 27
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...;> (which is currently reverted). The verification in question is:
>>>>
>>>> *** Bad machine code: Multiple connected components in live interval ***
>>>> - function: utils_la_suite_matmul_ref
>>>> - interval: %vreg77
>>>> [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r
>>>> 1 at 208B-phi 2 at 312r 3 at 380r
>>>> 0: valnos 0 1 3
>>>> 1: valnos 2
>>>>
>>>> In this particular case, I believe that it is the greedy allocator
>>>> that is creat...
2017 Sep 27
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...isters (which is currently reverted). The verification in question is:
>>>>>
>>>>> *** Bad machine code: Multiple connected components in live interval ***
>>>>> - function: utils_la_suite_matmul_ref
>>>>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>>>>> 0: valnos 0 1 3
>>>>> 1: valnos 2
>>>>>
>>>>> In this particular case, I believe that it is the greedy allocator that is creating the multiple co...
2012 Jun 12
2
[LLVMdev] Assert in live update from MI scheduler.
...reg9<def> = ADD_ri %vreg10, 8; IntRegs:%vreg9,%vreg10
128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
192B JMP <BB#2>
Successors according to CFG: BB#2 BB#1
208B BB#2: derived from LLVM BB %for.end
Predecessors according to CFG: BB#1
224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
pointer") IntRegs:%vreg7,%vreg1
240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
mem:ST4[@yy_instr](tbaa=!&q...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...g10, 8; IntRegs:%vreg9,%vreg10
> 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6 IntRegs:%vreg10
> 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> 192B JMP <BB#2>
> Successors according to CFG: BB#2 BB#1
>
> 208B BB#2: derived from LLVM BB %for.end
> Predecessors according to CFG: BB#1
> 224B %vreg7<def> = LDriw %vreg1<kill>, 0; mem:LD4[%first1](tbaa=!"any
> pointer") IntRegs:%vreg7,%vreg1
> 240B STriw_GP <ga:@yy_instr>, 0, %vreg7<kill>;
> mem...
2017 Apr 24
3
Debugging UNREACHABLE "Couldn't join subrange" in RegisterCoalescer (out-of-tree backend)
...quot;stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
Here's the tail-end of the log, with debugging turned on:
$llc bugpoint.reduced.simplified.bc -debug
...
208B %vreg13:sub_64_1<def> = COPY %vreg34:sub_64_1; VecRegs:%vreg13,%vreg34
Considering merging to VecRegs with %vreg34 in %vreg13
RHS = %vreg34 [160r,240r:0)[240r,384B:1)[400B,480r:1)[480r,496r:2)[496r,672r:3) 0 at 160r 1 at 240r 2 at 480r 3 at 496r L00000020 [240r,384...
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %1:tgpr
224B $r2 = COPY %2:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...
2017 Oct 13
2
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...em:LD8[%den](tbaa=!4)
G8RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4)
G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4)
G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
208B %vreg10<def> = LD 16, %vreg0;
mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
224B %vreg11<def> = LD 16, %vreg1;
mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1
272B %vreg13<def> = LD 24, %vreg0;
mem:LD...
2012 Jun 11
0
[LLVMdev] scoreboard hazard det. and instruction groupings
On Jun 11, 2012, at 12:07 PM, Hal Finkel <hfinkel at anl.gov> wrote:
> Looking at VLIWPacketizerList::PacketizeMIs, it seems like the
> instructions are first scheduled (via some external scheme?), and then
> packetized 'in order'. Is that correct?
Anshu?
> In the PowerPC grouping scheme, resources are assigned on a group
> basis (by the instruction dispatching
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp
160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp
192B $r0 = COPY %0:tgpr
208B $r1 = COPY %2:tgpr
224B $r2 = COPY %1:tgpr
240B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $s...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...EF; R600_Reg128:%vreg10
176B%vreg9<def,tied1> = INSERT_SUBREG %vreg10<tied0>, %vreg6<kill>, sel_x; R600_Reg128:%vreg9,%vreg10 R600_Reg32:%vreg6
192B%vreg11<def,tied1> = INSERT_SUBREG %vreg9<tied0>, %vreg8<kill>, sel_y; R600_Reg128:%vreg11,%vreg9 R600_Reg32:%vreg8
208B%vreg13<def> = IMPLICIT_DEF; R600_Reg32:%vreg13
224B%vreg12<def,tied1> = INSERT_SUBREG %vreg11<tied0>, %vreg13, sel_z; R600_Reg128:%vreg12,%vreg11 R600_Reg32:%vreg13
240B%vreg15<def> = IMPLICIT_DEF; R600_Reg32:%vreg15
256B%vreg14<def,tied1> = INSERT_SUBREG %vreg12<ti...
2012 Jun 13
4
[LLVMdev] Assert in live update from MI scheduler.
...; > 128B %vreg6<def> = CMPEQri %vreg10, 0; PredRegs:%vreg6
> IntRegs:%vreg10
> > 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>; PredRegs:%vreg6
> > 192B JMP <BB#2>
> > Successors according to CFG: BB#2 BB#1
> >
> > 208B BB#2: derived from LLVM BB %for.end
> > Predecessors according to CFG: BB#1
> > 224B %vreg7<def> = LDriw %vreg1<kill>, 0;
> mem:LD4[%first1](tbaa=!"any
> > pointer") IntRegs:%vreg7,%vreg1
> > 240B STriw_GP <ga:@yy_instr>, 0, %vr...
2012 Jun 11
3
[LLVMdev] scoreboard hazard det. and instruction groupings
On Mon, 11 Jun 2012 10:48:18 -0700
Andrew Trick <atrick at apple.com> wrote:
> On Jun 11, 2012, at 9:30 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> > I'm considering writing more-detailed itineraries for some PowerPC
> > CPUs that use the 'traditional' instruction grouping scheme. In
> > essence, this means that multiple instructions will stall
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...CMPEQri %vreg10, 0; PredRegs:%vreg6
> > IntRegs:%vreg10
> > > 176B JMP_cNot %vreg6<kill>, <BB#1>, %PC<imp-def>;
> PredRegs:%vreg6
> > > 192B JMP <BB#2>
> > > Successors according to CFG: BB#2 BB#1
> > >
> > > 208B BB#2: derived from LLVM BB %for.end
> > > Predecessors according to CFG: BB#1
> > > 224B %vreg7<def> = LDriw %vreg1<kill>, 0;
> > mem:LD4[%first1](tbaa=!"any
> > > pointer") IntRegs:%vreg7,%vreg1
> > > 240B STriw_GP <...
2017 Oct 13
3
Machine Scheduler on Power PC: Latency Limit and Register Pressure
...RC:%vreg3 G8RC_and_G8RC_NOX0:%vreg1
>> 144B %vreg7<def> = LD 8, %vreg0; mem:LD8[%arrayidx.1](tbaa=!4) G8RC:%vreg7 G8RC_and_G8RC_NOX0:%vreg0
>> 160B %vreg8<def> = LD 8, %vreg1; mem:LD8[%arrayidx2.1](tbaa=!4) G8RC:%vreg8 G8RC_and_G8RC_NOX0:%vreg1
>> 208B %vreg10<def> = LD 16, %vreg0; mem:LD8[%arrayidx.2](tbaa=!4) G8RC:%vreg10 G8RC_and_G8RC_NOX0:%vreg0
>> 224B %vreg11<def> = LD 16, %vreg1; mem:LD8[%arrayidx2.2](tbaa=!4) G8RC:%vreg11 G8RC_and_G8RC_NOX0:%vreg1
>> 272B %vreg13<def> = LD 24,...
2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...76B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
register: %vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vreg16<kill>; R600_Reg128:%vreg26 R600_TReg32:%vreg16
regist...