search for: 1d746cb3

Displaying 2 results from an estimated 2 matches for "1d746cb3".

2014 Jul 06
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
OK, so in you case, you want DAG.getSExtOrTrunc(SetCC, DL, SelectVT) to tunc the result from i64 to i32 on 64 bits targets, if I understand correctly. 2 questions: - Why not generating a selectcc node directly ? It avoid having to mess up with intermediate values. - Why calling getSetCCResultType(VT) ? VT is not the type of a parameter of setcc, and this looks incorrect to me. 2014-07-05 0:34
2014 Jul 08
2
[LLVMdev] LLVM commit 410f38e01597120b41e406ec1cea69127463f9e5
...at it did originally, and what I fixed. It now checks > getSetCCResultType of the operand's operand's value type, the setcc's > operand -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140707/1d746cb3/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Remove-loop-generation-in-DAGCombiner.patch Type: text/x-patch Size: 1069 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20140707/1d746cb3/attachment...