Displaying 2 results from an estimated 2 matches for "1b7321d2".
2017 Mar 11
2
Is there a way to know the target's L1 data cache line size?
Hi everyone,
I'm hailing from the Rust community, where there is a discussion about
adding facilities for aligning data on an L1 cache line boundary. One
example of situation where this is useful is when building thread
synchronization primitives, where avoiding false sharing can be a
critical concern.
Now, when it comes to implementation, I have this gut feeling that we
probably do not
2017 Mar 11
3
Is there a way to know the target's L1 data cache line size?
...>
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
> <http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev>
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170311/1b7321d2/attachment.html>