Displaying 6 results from an estimated 6 matches for "180h".
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2008 Jul 14
5
[LLVMdev] Spilled variables using unaligned moves
...his seems like an optimization opportunity.
The attached replacement of fibonacci.cpp generates x86 code like this:
03A70010 push ebp
03A70011 mov ebp,esp
03A70013 and esp,0FFFFFFF0h
03A70019 sub esp,1A0h
...
03A7006C movups xmmword ptr [esp+180h],xmm7
...
03A70229 mulps xmm1,xmmword ptr [esp+180h]
...
03A70682 movups xmm0,xmmword ptr [esp+180h]
Note how stores and loads use unaligned moves while it could use aligned
moves. It's also interesting that the multiply does correctly assume the
stack to be 16-byte aligned...
2008 Jul 14
0
[LLVMdev] Spilled variables using unaligned moves
...rtunity.
>
> The attached replacement of fibonacci.cpp generates x86 code like
> this:
>
> 03A70010 push ebp
> 03A70011 mov ebp,esp
> 03A70013 and esp,0FFFFFFF0h
> 03A70019 sub esp,1A0h
> ...
> 03A7006C movups xmmword ptr [esp+180h],xmm7
> ...
> 03A70229 mulps xmm1,xmmword ptr [esp+180h]
> ...
> 03A70682 movups xmm0,xmmword ptr [esp+180h]
>
> Note how stores and loads use unaligned moves while it could use
> aligned moves. It’s also interesting that the multiply does
> correctly assume...
2008 Jul 14
0
[LLVMdev] Spilled variables using unaligned moves
...-Chris
>
> The attached replacement of fibonacci.cpp generates x86 code like
> this:
>
> 03A70010 push ebp
> 03A70011 mov ebp,esp
> 03A70013 and esp,0FFFFFFF0h
> 03A70019 sub esp,1A0h
> ...
> 03A7006C movups xmmword ptr [esp+180h],xmm7
> ...
> 03A70229 mulps xmm1,xmmword ptr [esp+180h]
> ...
> 03A70682 movups xmm0,xmmword ptr [esp+180h]
>
> Note how stores and loads use unaligned moves while it could use
> aligned moves. It’s also interesting that the multiply does
> correctly assume...
2008 Jul 15
1
[LLVMdev] Spilled variables using unaligned moves
.... This seems like an optimization opportunity.
The attached replacement of fibonacci.cpp generates x86 code like this:
03A70010 push ebp
03A70011 mov ebp,esp
03A70013 and esp,0FFFFFFF0h
03A70019 sub esp,1A0h
...
03A7006C movups xmmword ptr [esp+180h],xmm7
...
03A70229 mulps xmm1,xmmword ptr [esp+180h]
...
03A70682 movups xmm0,xmmword ptr [esp+180h]
Note how stores and loads use unaligned moves while it could use aligned
moves. It's also interesting that the multiply does correctly assume the
stack to be 16-byte aligned...
2013 Jul 19
0
[LLVMdev] llvm.x86.sse2.sqrt.pd not using sqrtpd, calling a function that modifies ECX
...movaps xmm4,xmmword ptr [esp+1B0h]
002B075D mulpd xmm1,xmm4
002B0761 movaps xmm4,xmmword ptr [esp+240h]
002B0769 movaps xmm5,xmmword ptr [esp+1C0h]
002B0771 mulpd xmm4,xmm5
002B0775 movaps xmm5,xmmword ptr [esp+250h]
002B077D movaps xmmword ptr [esp+180h],xmm0
002B0785 movaps xmm0,xmmword ptr [esp+1D0h]
002B078D mulpd xmm5,xmm0
002B0791 addpd xmm5,xmm4
002B0795 addpd xmm5,xmm1
002B0799 movaps xmm0,xmmword ptr [esp+1A0h]
002B07A1 addpd xmm0,xmm5
002B07A5 movapd xmm1,xmmword ptr ds:[2B0020h]
002B0...
2013 Jul 19
4
[LLVMdev] SIMD instructions and memory alignment on X86
Hmm, I'm not able to get those .ll files to compile if I disable SSE and I
end up with SSE instructions(including sqrtpd) if I don't disable it.
On Thu, Jul 18, 2013 at 10:53 PM, Peter Newman <peter at uformia.com> wrote:
> Is there something specifically required to enable SSE? If it's not
> detected as available (based from the target triple?) then I don't think