Displaying 7 results from an estimated 7 matches for "176r".
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2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18
register: %vreg21 +[128r,176r:0)
144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
register: %vreg23 +[144r,224r:0)
160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15
register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0) ...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>;
> R600_Reg128:%vreg21 R600_Reg32:%vreg18
> register: %vreg21 +[128r,176r:0)
> 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19
> register: %vreg23 +[144r,224r:0)
> 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23
> R600_TReg32:%vreg15
> register: %vreg23 replace range with [144r,160r:1) RESULT:
&...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...= ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
register: %vreg8 +[144r,192r:0)
160B%vreg9:sel_x<def,read-undef> = COPY %vreg6<kill>; R600_Reg128:%vreg9 R600_Reg32:%vreg6
register: %vreg9 +[160r,176r:0)
176B%vreg11<def> = COPY %vreg9<kill>; R600_Reg128:%vreg11,%vreg9
register: %vreg11 +[176r,208r:0)
192B%vreg11:sel_y<def> = COPY %vreg8<kill>; R600_Reg128:%vreg11 R600_Reg32:%vreg8
register: %vreg11 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,208r:0) 0 at...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...se
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
register: %vreg2 +[112r,128r:0)
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
BB#3: # derived from return
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
register: %vreg4 +[160r,176r:0)
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B BB#0 R2#0
Created 1 new intervals.
********** INTERVALS **********
R2 = [0B,16r:0)[176r,192r:1) 0 at 0B-phi 1 at 176r
%vreg0 = [16r,32r:0) 0 at 16r
%vreg2...
2014 Dec 31
0
CentOS 6.6 - net-snmp process - Too many open files
...07 root 173r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 174r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 175r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 176r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 177r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 178r REG 0,3 0 4026532160
> /proc/26907/net/sctp/snmp
> snmpd 26907 root 179r REG...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2