Displaying 4 results from an estimated 4 matches for "16xi32".
Did you mean:
16x32
2018 Mar 20
1
Polly -polly-prevect-width
i musing polly with vec-width=16 default my IR emits <16xi32> and remaining
as <4xi32> by using polly. I want my IR to emit <16xi32> and remaining left
as <8xi32>. How to do this?
i m trying to use -polly-prevect-width.
please help.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org...
2018 Jul 24
2
KNL Vectorization with larger vector width
Hello,
I need help here. I am able to adjust the vector width through
WidestRegister value. When number of iterations=31 and I set vector
width=32 it gives <16xi32> and <8xi32> instructions.
However if i replicate same behavior with number of iterations=63 and I
set vector width=64, no vector instructions are emitted. it should do as
previous and gives <32xi32> and <16xi32> vector instructions.
How to do this?
What adjustments are need...
2018 Jul 24
2
KNL Vectorization with larger vector width
Thank You.
Right now to see the effect i did following changes;
unsigned X86TTIImpl::getRegisterBitWidth(bool Vector) {
if (Vector) {
if (ST->hasAVX512())
return 65536;
here i changed 512 to 65536. Then in loopvectorize.cpp i did following;
assert(MaxVectorSize <= 2048 && "Did not expect to pack so many elements"
" into
2018 Jul 23
2
KNL Vectorization with larger vector width
...gt; etc.
How to achieve this? Please help.
Thank You
Regards
On Fri, Jul 13, 2018 at 12:40 AM, Hal Finkel <hfinkel at anl.gov> wrote:
>
> On 07/12/2018 02:32 PM, hameeza ahmed via llvm-dev wrote:
>
> Hello,
>
> If we pass march=knl, the llvm vectorizer (O3) generates max 16xi32 vector
> width instruction and 8xi32 or 4xi32 in recursive manner.
>
> I am working on a target with larger vector widths like 32,64...
> Now how to enable the vectorizer (O3) to automatically generate larger
> vector size instructions recursively by specifying the new target. Which...